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Final Exam: Wednesday August 16, 9:45 AM
BLDG 8 Room 1300
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Thursday, 18-Mar-2010 17:02:45 EDT
1774
Visitors Since 5-June-2000
 
Assignment #1, Due Monday, June 19.
Assignment #2, Due Monday, June 26.
Assignment #3, Due Wednesday, July 5.
Assignment #4, Due Wednesday, July 26.
Assignment #5, Due Wednesday, August 2.
Assignment #6, Due Wednesday, August 9.
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For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:
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6-5-2K
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Introduction to Computer Design, The Design Hierarchy, Technology Trends,
Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
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6-7-2K
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MIPS Instruction Set Architecture, Examples, Instruction Formats & Encoding.
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6-12-2K
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Computer Performance Measures: CPI, CPU Execution Equation, Benchmarking, Amdahl's Law.
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6-14-2K
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MIPS Single Cycle Datapath & Control Unit Design.
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6-19-2K
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MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
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6-26-2K
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Microprogrammed CPU Control, Exception Handling.
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7-5-2K
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Integer ALU Design, Floating Point Computations.
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7-10-2K
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Midterm Review.
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7-17-2K
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Instruction Pipelining, Pipeline Hazards, Forwarding.
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7-24-2K
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The Memory Hierarchy; Basic Cache Design Issues& Cache Performance.
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8-2-2K
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The Memory Hierarchy: Main & Virtual Memory.
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8-7-2K
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Input/Output Organization, Design Considerations & Performance.
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8-9-2K
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Final Exam Review.
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Monday, Wednesday 3:00-4:50 PM Bldg. 76, Room 1155
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 he course covers the important aspects of the design,
organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture
classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic
unit design, and the memory hierarchy, including cache levels and virtual memory.
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Assembly Programming EECC250, Introduction to Digital Systems EECC341, Operating Systems (0603-440).
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Participation and class presence: 5%
Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 25%
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Attending all lecture sessions is expected.
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1- Introduction: Modern Computer Design Levels, Components, Technology Trends.
2- Instruction Set Architecture (ISA) Characteristics.
3- CPU & Computer System Performance Measures.
4- Hardware Description: Register Transfer Notation (RTN).
5- Central Processor Organization: Datapath & Control Unit Design.
6- Microprogrammed Control Unit Design.
7- Computer Arithmetic & ALU Design.
8- CPU Pipelining.
9- The Memory Hierarchy.
10- I/O Organization: Interfacing Processors and Peripherals.
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