Computer Organization

EECC 550 Summer 1999

MY HOME PAGE RIT Computer Engineering
Final Exam:  Tuesday August 17th, 9:45 AM
BLDG 12   Room 1125

Monday, 21-May-2012 06:38:27 EDT

1231 Visitors Since 7-June-1999


  

  Assignment #1, Due Wednesday, June 23.

  Assignment #2, Due Monday, July 19.

  Assignment #3, Due Monday, August 2.

  Assignment #4, Due Monday, August 9.

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

6-7-99 Introduction to Computer Design, The Design Hierarchy, Technology Trends, Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
6-9-99 MIPS Instruction Set Architecture, Examples, Instruction Formats & Encoding.
6-14-99 Computer Performance Measures: CPI, CPU Equation, Benchmarking, Amdahl's Law
6-21-99 Design of an Accumulator Machine (TM-16, handout)
6-28-99 MIPS Single Cycle Datapath & Control Unit Design
6-30-99 MIPS Multicycle Datapath and Finite State Machine Control Unit Design
7-5-99 Microprogrammed Control, Exception Handling
7-12-99 Midterm Review
7-21-99 ALU Design, Floating Point Computations
7-28-99 Instruction Pipelining, Pipeline Hazards
8-2-99 The Memory Hierarchy; Basic Cache Design & Performance
8-4-99 The Memory Hierarchy: Main & Virtual Memory
8-11-99 Final Review
Get Adobe Acrobat


  

Monday, Wednesday 3:00-4:50 PM Bldg. 8, Room 2300


  

Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373


Office Hours:
My Summer 99 schedule


  

Current: http://www.rit.edu/~meseec/eecc550-summer99/
Summer 98: http://www.rit.edu/~meseec/eecc550-summer98/
Summer 97: http://www.rit.edu/~meseec/eecc550/


  

The course covers important aspects of the design and organization of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy.


  

Introduction to Digital Systems EECC341, Operating Systems (0603-440).


  

Computer Organization & Design: The Hardware/Software Interface, Second Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 1998


  

Participation and class presence: 5%
Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 25%


  

Attending all lecture sessions is expected.


  

1- Introduction: Modern Computer Design Levels, Components, Technology Trends.
2- Instruction Set Architecture (ISA) Characteristics.
3- CPU & Computer System Performance Measures.
4- Hardware Description: Register Transfer Notation (RTN).
5- I/O Organization: Interfacing Processors and Peripherals.
6- Central Processor Organization: Datapath & Control Unit Design.
7- Microprogrammed Control Unit Design.
8- Computer Arithmetic & ALU Design.
9- The Memory Hierarchy.
10- CPU Pipelining.

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