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Final Exam: Monday, February 23, 12:30-2:30PM
Building 9 Room 3129
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Monday, 23-Nov-2009 04:45:21 EST
1617
Visitors Since 30-Nov-2008
 
For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:
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12-2-2K8
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Introduction to Computer Design, The Design Hierarchy, Technology Trends, Register Transfer Notation (RTN),
Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
(Chapters 1, 2)
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12-4-2K8
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MIPS RISC Instruction Set Architecture: Syntax, Addressing Modes, Instruction Formats, Encoding & Examples.
(Chapter 2)
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12-9-2K8
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Central Processor Unit (CPU) & Computer System Performance Measures: CPI, CPU Execution Equation, Benchmarking, MIPS Rating,
Amdahl's Law.
(Chapter 4)
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12-16-2K8
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CPU Design: MIPS Single Cycle Datapath, Control Unit Design.
(Chapter 5.1-5.4)
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1-6-2K9
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CPU Design: MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
(Chapter 5.5)
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1-13-2K9
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Microprogrammed CPU Control Design for MIPS. Exception Handling.
(Microprogramming: 5.7,
Appendix C.
Exception Handling: Chapter 5.6)
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1-15-2K9
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CPI Reduction: CPU Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding. Compiler Instruction Scheduling.
Delayed Branch. Pipelined CPU Performance.
(Chapter 6.1-6.6)
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1-22-2K9
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Midterm Review.
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2-3-2K9
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Removing The Ideal Main Memory Assumption. The Memory Hierarchy: Basic Cache Design & Performance.
(Chapter 7.1-7.3)
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2-17-2K9
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Input/Output & System Performance Issues. (FYI)
(Chapter 8)
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2-19-2K9
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Final Exam Review.
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Tuesday, Thursday 2:00-3:50PM Building 9 Room 3129
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 he course covers the important aspects of the design,
organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture
classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic
unit design, and the memory hierarchy, including cache levels and virtual memory.
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Assembly Programming EECC250, Introduction to Digital Systems EECC341, Operating Systems (0603-440).
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Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 30%
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Attending all lecture sessions is expected.
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1- Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Notation (RTN). [Chapters 1, 2]
2- Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2]
3- MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2]
4- Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4]
5- CPU Organization: Datapath & Control Unit Design. [Chapter 5]
6- Microprogrammed Control Unit Design. [Chapter 5]
7- CPU Pipelining. [Chapter 6]
8- The Memory Hierarchy: Cache Design & Performance. [Chapter 7]
9- The Memory Hierarchy: Main & Virtual Memory. [Chapter 7]
10- Input/Output Organization & System Performance Evaluation. [Chapter 8]
11- Computer Arithmetic & ALU Design. [Chapter 3]
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