My interests as a researcher have been traditionally focused in three areas: nanoelectronic devices and circuits, photonic/optoelectronic devices/circuits, and advanced semiconductor fabrication techniques. Prior to joining RIT in July 2002, I received my Ph.D. at the University of Delaware and worked as a postdoctoral research assosciate at the University of Illinois at Urbana-Champaign. My Ph.D. dissertation demonstrated Si tunneling diodes which could operate at room temperature and could be integrated into a CMOS fabrication process. This project was funded by the DARPA Ultrananoelectronics Initiative as part of the QMOS project managed by Raytheon Systems Company. The project had an immediate impact on the industry. Our team received the 1998 DARPA Ultrananoelectronics Program Award of Excellence for demonstrating a method of integrating a Si tunnel diode in a CMOS circuit that operated at room temperature. The work was also a major catalyst for the organization of the SRC Workshop on Si Tunnel Diode and CMOS/HBT Integration Workshop in Washington, DC ( December 9, 1999). My dissertation entitled "Si-based Tunneling Diodes for Integrated Circuit Applications" was also awarded the 2000 Allan P. Colburn Prize for Dissertation in Engineering and Mathematical Sciences by the University of Delaware. At the University of Illinois at Urbana-Champaign, my project was to develop a fabrication process to realize low-loss InP-based waveguide structures as part of the DARPA RFLICs program. While at the UIUC, I had the opportunity to work with two electron beam lithography tools: a Leica 10.5 EBMF and a JEOL 6000FS. These activities are highlighted below:
RIT has recently received funding in conjunction with Amberwave Systems (Salem NH) from the National Science Foundation to fabricate Esaki diodes in Ge and III-V materials on a Si substrate. Amberwave has developed an approach known as Aspect Ratio Trapping (ART) to localize threading and misfit dislocations due to lattice mismatch from Si within oxide openings. III-V and Ge offer much higher performance tunnel diodes compared to Si due to their differing band structures. Recently the team at RIT has published a study demonstrating an alloyed junction Ge Esaki diode on a Si subtrate. The team is also presently pursuing the realization of III-V Esaki diodes on Si substrates, and hopes to report on them soon.
Recently the Rochester Institute of Technology has demonstrated the co-integration of CMOS devices and resonant interband tunnel diodes (RITDs). Our strategy has been to integrate the tunnel diodes following all high temperature steps, but prior to the contact metallization of the CMOS devices. A recent paper in the Sept. 2003 issue of IEEE Transactions on Electron Devices co-written by our sister group at the Ohio State University found that compared to the performance of bulk RITDs used as a control (with a peak-to-valley current ratio or PVCR of 3.8), the integrated devices exhibited a slight degradation performance (PVCR of 3.4). We have also published a paper at the University-Government Industry Microelectronics Conference (UGIM 2003) that showed a slight reduction in performance for integrating atop implant regions. When formally integrated atop CMOS, the PVCR ultimately was found to be 2.8. Details of this work were presented in Washington, DC at the 2003 ISDRS conference. We also have recently demonstrated a simple latch-based circuit in the form of a MOnostable BIstable Logic Element (MOBILE) incorporating an integrated FET and RITD. We believe that the MOBILE serves as a proof of concept, providing a roadmap as to the biasing conditions where the tunnel diode will ultimately be useful with CMOS.
In order to ensure that the tunnel diodes properly latch, we observe that a supply voltage on the order of 1 V- 0.5 V is required, or less. What is significant about this? When we first began working on tunnel diodes back in the late 90's, typical CMOS supply voltages were much higher. It would not have been practical to consider integration at that time. This work was also published at the ISDRS, and was published in Solid State Electronics. Additional studies are underway, and we anticipate submitting publication to various journals in the near future.
I have been repeatedly asked "How small can you build a tunnel diode"? We have also been asked several times about surface leakage currents. To date, I am not sure quite how small we can go, but I strongly believe that we can build a device that will fit exactly into the contact cut of modern CMOS devices (100nmx100 nm). With regard to surface leakage currents, we have not seen a strong area dependence on our diodes. Further we observe that we we make our diodes smaller, they get better. At the 2004 DRC, we published a study illustrating the effects of building a diode that is grown over the opening of the oxide, and is not completely etched away. We found that the transition between crystalline/non-cyrstalline structures was quite abrupt (substantially less than 10 nm).
Several folks have also asked how an RITD will perform at an elevated temperature of 100oC. The answer to this question (which we will soon publish in a more formal context) is very well! Recent data from our group in the summer of 2005 does show a dependence of the valley current on substrate temperature, but does simultaneously illustrate that it is extremely feasible to have a PVCR of ~3 even at 100oC. PVCR varies almost linearly with increased substrate temperature.
I first became involved in this work during my Ph.D. work at the University of Delaware under the guidance of Prof. Paul R. Berger, I worked on the development of Si-based Resonant Interband Tunneling Diodes in conjunction with Dr. Phillip E. Thompson and Dr. Karl Hobart of the United States Naval Research Laboratory (Washington, DC) as well as Dr Roger Lake (presently at UC Riverside) and Alan C. Seabaugh (presently at Notre Dame) of Raytheon Systems Company (Dallas, TX). As studies with III-V RTDs have shown, any transistor technology can be enhanced by the incorporation of a tunnel diode (For a comprehensive review, see Seabaugh, et al., 1998 IEDM Technical Digest, pp. 428-432, 1998) One such application is a 1-T low power static memory circuit which uses the negative differential resistance (NDR) of tunnel diodes to latch into a memory state (see van der Wagt, et al., IEEE Elec. Dev. Lett., pp. 7-9, 1998). Recently Prof. Seabaugh's group has published articles on another flavor of Si-based tunnel diodes formed by a proximity rapid thermal anneal.
Our first paper on the topic appeared in Applied Physics Letters on October 12, 1998 (pp. 2191-2193). [PDF File (71 KB)] . In this article, we describe a low temperature growth process which produced room temperature negative differential resistance after heat treatment in a rapid thermal annealing (RTA) furnace. The RTA temperature was found to have a dramatic influence on the current density of the resulting device.
The device structure presented in the letter incorporated a pair of Sb and B delta-doping planes at fixed offsets from an intrinsic Si0.5Ge0.5 tunnel barrier. The delta doping planes act to create quantum confined states in the valence and conduction bands which carriers tunnel from. The structure, therefore, may be viewed as a hybrid between an Esaki diode and a resonant tunnel diode called a resonant interband tunnel diode (RITD). Variations in the offset of the delta doping planes and the SiGe layer also influenced the device performance. At the 1998 IEDM meeting in San Francisco, we recently presented some additional Si-based tunnel diode designs which also exhibit room temperature NDR (see Rommel, et al., 1998 IEDM Technical Digest, Late News!, pp. 1035-1037 (1998))[PDF FILE (658 KB)].
Our group has also published two other papers on Si RITD structures. The first structure was in essence the same as the structure presented in our first letter without SiGe. This structure is discussed in an IEEE Electron Device Letters paper from July, 1999 (pp. 329-331) [PDF File (75 KB). The second paper was written by my colleague at NRL, Phil Thompson. This revised RITD structure with reduced doping in the bulk regions is discussed in an Applied Physics Letters article from August 30, 1999 (pp. 1308-1310) [PDF File (46 KB)].
In 1999-2000, work by Duschl et al. from the Max Planck Institute in Stuttgart, Germany based on our structure have broken the world record in peak-to-valley ratio, achieving a PVCR as high as 6! When comparing our old work with their work, we learned that they were using P as the n-type dopant, whereas our original work utilized Sb. In 2000, Phil Thompson added a P-cell to his MBE, which seems to have done the trick. Our group now routinely achieves PVCRs in the neighborhood of 3.8.
There have also been some other key studies in the past few year by other groups. In 2000-2002, a Si/SiGe n-type RTD was reported by D.J. Paul's group in Cambridge, UK. In a recent issue of Electron Device Letters as well as the 2004 Device Research Conference, a group from Korea built a 3-terminal tunnel diode. They reported a Si-only structure with a PVCR of 5.45.
The above figure shows an InP/InGaAsP ring resonator I fabricated while working at the University of Illinois. The sample was patterned by electron-beam lithography and etched in a Cl2/Ar/H2 plasma. We estimated the surface roughness to be less than 20 nm. This is critical for the fabrication of low-loss waveguides, as surface roughness leads to scattering losses. The etching process I developed is described in greater detail in an the Journal of Vacuum Science and Technology B (Jul/Aug. 2002 issue, SL Rommel, et. al).
Electronic Mail: slrommel@ieee.org
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Last Updated: July 21, 2008
Copyright 2008 Sean L. Rommel
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