Selected Publications

Publications in Refereed Journals

  1. S.H. Tavva, D.Kudithipudi, “Characterization of Variation Aware Nanoscale SRAM Designs”, J. Low Power Electronics , Vol. 6, N°1, April 2010.
  2. D. Kudithipudi and E. John, "Characterization of Adder circuits in Nanotechnology Designs", International journal of Embedded Systems, Volume 4, Number 1 / 2009, Pages:  17 – 26, 2009.
  3. D.Kudtihipudi,S.Petko, and E.John, “Caches for Multimedia Workloads: Power and Energy Trade-offs”, IEEE Transactions on Multimedia, Vol. 10(6), pp: 1013-1021 (2008).
  4. D. Kudithipudi and E.John, "Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells”,J. Low Power Electronics 3, 293–301 (2007).
  5. D. Kudithipudi and E.John,” Implementation of Low Power Digital Multipliers using 10 transistor Adder Blocks”, J. Low Power Electronics 1, 286-296 (2005).

Publications in Conferences

  1. C.Merkel, D.Kudithipudi, " Lightweight Energy Prediction Filters for Solar-Powered Wireless Sensor Networks", In proceedings of 6th International Workshop on Unique Chips and Systems, ( Held in Conjunction with IEEE MICRO)Georgia Tech, Atlanta, GA, 2010
  2. S. Amarchinta, D. Kudithipudi, “Ultra Low Energy Standard Cell Design Optimization For Performance and Placement Algorithm”, Workshop on Work in Progress in Green Computing, Chicago, Aug 16-18, 2010.
  3. A.Kwasinski, D. Kudithipudi, “Towards Integrated Circuit Thermal Profiling for Reduced Power Consumption: Evaluation of Distributed Sensing Techniques”, Workshop on Work in Progress in Green Computing, Chicago, Aug 16-18, 2010.
  4. S.H.Tavva, D.Kudithipudi, “Variation Tolerant 9T SRAM Cell Design”, ACM Great Lakes Symposium on VLSI 2010, Providence, Rhode Island, May 16-18, 2010.
  5. S.Amarchinta, J.Moon, and D.Kudithipudi, “Performance Enhancement Of Subthreshold Circuits Using Substrate Biasing And Charge-Boosting Buffers”, ACM Great Lakes Symposium on VLSI 2010, Providence, Rhode Island, May 16-18, 2010.
  6. K.F.Ng, K.Hsu, D.Kudithipudi, “A Parallel-Segmented Architecture for Low Power Content-Addressable Memory“, IEEE International System on Chip Conference (SOCC-2009), Belfast,North Ireland,UK, Sep. 9-11, 2009.
  7. M.N.Michael, D.Kudithipudi, “DVFS with Multi-Clock Distribution Systems on SPARC Core “, 4th Annual Austin Conference on Integrated Systems & Circuits 2009, Austin, Texas, Oct 26-27,2009.
  8. S. Amarchinta, H. Kanitkar and D. Kudithipudi, “Robust and High Performance Subthreshold Standard Cells”, in proc. 52nd IEEE Midwest Symposium on Circuits and Systems (MWCAS), Aug. 2009.
  9. H.Kanitkar and D. Kudithipudi, “Subthreshold Design space exploration of  a Guassian Normal Basis Multiplier”, in proceedings of IEEE Workshop on Unique Chips and Systems, Boston, April 2009.
  10. S. Katrue and D.Kudithipudi, “GALEOR: Leakage Reduction Technique for CMOS Circuits, proceedings of 15th IEEE International Conference on Electronics, Circuits and Systems, Malta, August 2008.
  11. D. Kudithipudi and E.John, “On Estimation of Static Power-Performance in TCAM”, in proc. 51st IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2008, pp. 783-786.
  12. B.Baylav, L.Fuller, D.Kudithipudi, “A New Test Chip for CMOS Manufacturing Laboratory Courses at RIT”, in proc. of 17th Biennial University/Government/Industry Micro/Nano Symposium,  Louisville, Kentucky, UGIM 2008.
  13. D. Kudithipudi, P.Nair, and E.John, “On Estimation and Optimization of Leakage Power in CMOS Multipliers”, in proc. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2007, pp. 859-862.
  14. V.Chinta and D.Kudithipudi, “Minimum Leakage Vector Pattern Estimation”, in proc. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2007, pp. 1066-1069.
  15. D. Kudithipudi and E. John, "Parametrical Characterization of leakage power in Nanoscale Technologies", IBM's Austin Conference on Energy Efficient Design, July 2005.
  16. D. Kudithipudi and E.John, "Parametrical Characterization of Leakage Power in Embedded System Caches using Gated-Vss", proceedings of International Association of Technology and Education for Circuits and Systems, Marina Del Rey, LA, pp: 493–076, October 2005.
  17. D. Kudithipudi and E. John, "A Combinatorial Approach to Suppress Leakage in Nanoscale SRAM cells", proceedings of IEEE Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, August 2005.
  18. D. Kudithipudi and E. John, "Parametrical Characterization of leakage power in Nanoscale Technologies", IBM's Austin Conference on Energy Efficient Design, July 2005.
  19. D.Kudithipudi and E.John, "A framework to moderate leakage power in nanoscale CMOS SoC devices", Nano Summit Research Conference, Houston, March 2005.
  20. D. Kudithipudi, S. Petko, and E. John, "Cache Leakage Power Analysis in Embedded Applications", proceedings of IEEE Midwest Symposium on Circuits and Systems, Hiroshima, Japan, Vol. II, pp.517–520, July 2004.
  21. S. Petko, D. Kudithipudi and E. John, "Memory System Characterization for Multimedia Applications", proceedings of International Signal Processing Conference (ISPC), Dallas, TX. March 31–April 3, 2003