Home Biography Research Low Power Lab Courses Publications Resources			Selected Publications D. Kudithipudi, S. Petko, and E.John, "Caches for Multimedia Workloads: Power and Energy Trade-offs", IEEE Transactions on Multimedia, accepted. S.Katrue and D.Kudithipudi, "GALEOR: Leakage Reduction Technique for CMOS Circuits",in Proceedings of ICECS 2008, August 2008. B. Baylav, L.Fuller, and D.Kudithipudi, "A New Test Chip for CMOS Manufacturing Laboratory Courses at RIT", UGIM 2008 (University Government Industry Micro/nano) Symposium,July 13-16, 2008. D. Kudithipudi and E. John, "Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells",J. Low Power Electronics 3, 293–301 (2007) D.Kudithipudi, P.Nair, and E.John, "On Estimation and Optimization of Leakage Power in CMOS Multipliers", proceedings of IEEE Midwest Symposium on Circuits and Systems–2007, Montreal, Canada, August 2007 V.Chinta and D.Kudithipudi, "Minimum Leakage Vector Pattern Estimation", proceedings of IEEE Midwest Symposium on Circuits and Systems-2007, Montreal, Canada, August 2007 D. Kudithipudi and E. John, "Characterization of Adder circuits in Nanotechnology Designs", International journal of Embedded Systems, to appear in 2007 issue D. Kudithipudi and E.John, "Implementation of Low Power Digital Multipliers using 10 Transistor Adder Blocks", J. Low Power Electronics 1,286–296(2005) S.Eratne, D.Kudithipudi, and E.John, "Integrated Performance Analysis of Full Adders in Nanoscale CMOS", IEEE Regional conference, April 2006. D.Kudithipudi and E.John, "Parametrical Characterization of Leakage Power in Embedded System Caches using Gated-Vss", proceedings of International Association of Technology and Education for Circuits and Systems, Marina Del Rey, LA, pp: 493–076, October 2005. D. Kudithipudi and E. John, "A Combinatorial Approach to Suppress Leakage in Nanoscale SRAM cells", proceedings of IEEE Midwest Symposium on Circuits and Systems-2005, Cincinnati, Ohio, August 2005. D. Kudithipudi and E. John, "Parametrical Characterization of leakage power in Nanoscale Technologies", IBM's Austin Conference on Energy Efficient Design, July 2005. D.Kudithipudi and E.John, "A framework to moderate leakage power in nanoscale CMOS SoC devices", Nano Summit Research Conference, Houston, March 2005. D. Kudithipudi, R. Kotha, E. John, and Z. P. Tanner, "Power, Performance and delay analysis of Multipliers in Nanoscale technologies", proceedings of International Signal Processing Conference, Santa Clara, CA, October 2004. D. Kudithipudi, S. Petko, and E. John, "Cache Leakage Power Analysis in Embedded Applications", proceedings of IEEE Midwest Symposium on Circuits and Systems, Hiroshima, Japan, Vol. II, pp.517–520, July 2004. S. Petko, D. Kudithipudi and E. John, "Memory System Characterization for Multimedia Applications", proceedings of International Signal Processing Conference (ISPC), Dallas, TX. March 31–April 3, 2003 M. Wasiewicz, D. Kudithipudi and E. John, "Low Power Parallel Digital Multipliers using 10 Transistor Adder Circuits", proceedings of International Signal Processing Conference (ISPC), Dallas, TX. March 31–April 3, 2003 S. Petko, D. Kudithipudi and E. John, "Cache Performance of Video Computation Workloads", proceedings of third International workshop on Digital and Computational video, DCV 2002, pp: 169–175, November 2002.