This is a research project sponsored by Hewlett-Packard, Boise, ID. It is reviewed, and pending approval continued, on a yearly basis. We investigate the tradeoffs in implementing image processing systems in ASICs and FPGAs. For the latter, we focus on the possibility of overlapping reconfiguration and processing time. In 2010-2011 Dr. Peskin was PI and Dr. Saber and myself CO-PIs. During 2011-2012 I became PI and Dr. Saber CO-PI. .

This is a research project sponsored by Hewlett-Packard, Boise, ID. It is reviewed, and pending approval continued, on a yearly basis. We investigate the tradeoffs in performing parallel image processing in software using SIMD instruction set extensions. During 2011-2012 I was PI and Dr. Saber CO-PI.

Since July 2008, Dr. Patru is investigating a computer architecture for late and post silicon technologies. The architecture is tolerant to device and component failures, while at the same time allows for massive parallel and concurrent computing. During 2008-2009, two graduate students, Jesse Muszynski and Adam Spirer, have developed the first versions of a functional simulator and compiler for this architecture. During 2012-2013 Holden Sandler, currently a graduate student, is continuing the work on the C to SOAP compiler. A journal paper describing the organization, operation and characteristics of this architecture is currently under review.

Beyond teaching, Project METEOR has been Dr. Patru's and Dr. Kozak's (ME) focus between Fall 2003 and Spring 2008. For more information visit http://meteor.rit.edu.

The "Pipelined Interconnect Free Logic" is a gate level design methodology that uses only relatively short, next gate interconnections. It is intended to address the increasing delay due to interconnect parasitics at GHz frequencies and in nanometer semiconductor technologies. The computer architecture Dr. Patru and his current graduate students are investigating (research topic 1 above), addresses and resolves the interconnect problem at the system level. Still, the application of this methodology remains attractive for data driven computing algorithms. For more information see the publications list.

"Optically Injected Logic Circuits" require no wired power supply. The power is supplied at the time of operation via an optical beam. The optical energy is converted into electrical energy in each node of the circuit, making the need of a power supply circuit and power distribution grid unnecessary. Remote power is traditionally delivered using inductive coupling. The main advantage of the optically injected logic circuits is the distance between the energy provider and the remote powered device. The distance is virtually limited by the line of sight and the power of the optical beam. The performance of these circuits is estimated to improve at every nanometer technology node. This research is an offspring of Dr. Patru's PhD thesis research.

Please check the experience link.