Text Box: Workshop on
Energy-efficient Networks of Computers (E2NC): from the Chip to the Cloud 

Collocated with International Green and Sustainable Computing Conference, 2017

As part of the IEEE International Green and Sustainable Computing conference, a special workshop termed Energy-efficient Networks of Computers: from the Chip to the Cloud (E2NC) will be organized to address various design aspects of power efficient and dependable computing infrastructures from the perspective of the interconnection networks. Computing machinery around the world consumes staggering amounts of energy. The increasing power consumption of Integrated Circuits has plagued the semiconductor industry for years. Soaring power dissipations have proved to be the limiting factor for increase in performance. Complex digital integrated circuits consisting of multiple components or cores form the underlying hardware for these massive computing infrastructures. Warehouse-scale computers powered by such multicore chips have applications in several important domains ranging from scientific applications like weather or economic forecasting, astronomical data analysis, bioinformatics applications to even consumer electronics. Graphics Processing Units (GPUs) and General Purpose GPUs (GPGPUs) and heterogeneous systems with CPUs, GPUs, memories and programmable fabrics provide the computational backbone for not only graphics based application but many data parallel tasks as well. The Internet of Things (IoT) with billions of connected devices pose new challenges to the problem of connectivity and scale. All these computing infrastructures consist of interconnected or networked components. The role of the interconnection therefore becomes paramount in determining the performance and efficiency of these hardware. In addition the reliability and security of these networked computing modules will also determine their sustainability and suitability in the near and distant future. This workshop will encompass a broad range of topics related to power efficiency and dependability of modern interconnected computing machinery at various scales from multicore chips to IoT, datacenters and the cloud. Its objective is to facilitate exchange of valuable information and ideas among researchers and practitioners. The workshop will consist of invited presentations and peer-reviewed research papers. The topics of interest include, but are not limited to, the following:

Text Box: Energy-Efficient Networks-on-Chips
Energy-Efficient Interconnections for multi-chip systems such as servers
Energy-efficiency in IoT devices
Emerging interconnect technologies
Energy-efficiency of Datacenter Networks 
Power-Efficient HPCs/Data Centers 
Energy-Efficient Sensor Networks
Low-overhead Security and DoS issues for interconnection networks
Temperature-aware methodologies to improve reliability and sustainability of computing infrastructure
Power/Energy efficiency of GPU or heterogeneous systems.

Author Information:

Full papers following the guidelines of the International Green and Sustainable Computing (IGSC) are sought. All papers should be submitted electronically (in PDF format) using the instructions at the E2NC website. All submitted/invited manuscripts will be reviewed and evaluated on correctness, originality, technical strength, significance, quality of presentation, interest, and relevance to the scope of the workshop.

   Papers presented at the workshop will be published in the official conference proceedings (through IEEE Digital Library-IEEE Explore) contingent on two conditions: (1) One author of each accepted paper must register for the conference at the time of the submission of the accepted final manuscript and (2) One of the authors must appear to present the paper at the workshop. Please note that each accepted workshop paper will require a full IGSC registration at the IEEE member or at the non-member rate (NOT student rate). There will be no separate workshop-only registration.


Submission Link:  Please use the specific track for “Workshop on Energy-efficient Networks of Computers (E2NC)” while submitting the paper using the easychair link for IGSC 2017. The IGSC 2017 submission links can be found here. It is also available on the IGSC website.


Submission Due: August 25, 2017

Notification of Acceptance: September 15, 2017

Camera-ready paper due: September 22, 2017.


Workshop Organizers:

Amlan Ganguly, Rochester Institute of technology

Please direct questions regarding this workshop to Amlan Ganguly (amlan.ganguly@rit.edu).