ELECTRICAL & MICROELECTRONIC ENGINEERING DEPARTMENT

OF THE

KATE GLEASON COLLEGE OF ENGINEERING

ROCHESTER INSTITUTE OF TECHNOLOGY

 

Course Outline

Revision Date: 3/08/10

 

 

Catalog: EMCR350 IC TECHNOLOGY / MICROELECTRONICS I

QTR: 093      Registration # 0305 350/701

 

COURSE LEVEL:   2nd year undergrad / 1st year grad student

 

PREREQUISITES:   Introduction to Microelectronics (EMCR201)

 

INSTRUCTOR:   Karl Hirschman, Office 17-2645, x5130, kdhemc@rit.edu

 

LAB ASSISTANTS:   Ryan Rettmann & Andrew McCabe

 

 

TEXTBOOK:   Introduction to Microelectronic Fabrication by Richard C. Jaeger,  

Addison-Wesley, 1993

 

REFERENCES:  Microchip Manufacturing by Stanley Wolf, Lattice Press, 2004

 

 

COURSE DESCRIPTION & OBJECTIVES:

 

0305-350 is an introduction to the physics, chemistry and materials of integrated circuit fabrication.  The course provides a hands-on device fabrication and characterization experience, from CAD design through electrical test.  Students gain an understanding on what goes into the design of a basic process flow, and the structural design of devices.  They also investigate how a CAD design (layout) is translated into silicon devices and circuits. 

 

Topics include the basic process steps of crystal growth, oxidation, photolithography, diffusion, ion implantation, chemical vapor deposition (CVD) and metallization used to build integrated circuits.  Mathematics and physics are used to develop process models; closed-form calculations are compared to numerical simulation results (SUPREM) and in-process measurements.  The laboratory uses a 4-level metal gate PMOS process to fabricate a working integrated circuit testchip and provide experience in device design, process design, materials evaluation, in-process characterization and device testing.

 

 

 

TOPICS:

        Material and Electrical Properties of Si

        Overview of IC processing

        RIT PMOS process (laboratory)

        Crystallography  -  (crystal structure, growth, wafer fabrication)

        Impurity Diffusion in Si

        Thermal Oxidation of Si

        Ion Implant

        Semiconductor Devices

        Process Simulation (Athena SUPREM)

 

 

SCHEDULE:

        Lecture: M,T,R     9-10am   9-3149

        Lab:        M 1-4PM,  W 9AM-Noon ,  W 2-5PM

        Recitation & Office Hours:  T.B.D.

 

 

GRADING PERCENTAGES:

        Homework    10%

        Laboratory  25%

        5 Quizes (25min, drop lowest score)   40%

        Comprehensive Final Exam 25%