Course Outline



Department of Microelectronic Engineering


0305-520 VLSI DESIGN


2002-2003 Catalog Data:


0305-520 is an introduction to the design of CMOS very large scale integrated (VLSI) circuits, with an emphasis on details related to fabrication and circuit performance.  Topics include CMOS process technology, logic gate operation, logic design methodologies, circuit simulation (SPICE), design layout, system timing, subsystem design (ALUs, finite state machines, memory) and performance issues.  The laboratory will utilize Mentor Graphics design package running on HP-UNIX workstations.  Design tools include schematic capture, circuit simulation, design layout, design rule checking and layout vs. schematic.  Laboratory assignments will familiarize the students with the design tools, which will be used extensively for a moderately complex design project.




J.P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons, 2002.




Dr. Karl D. Hirschman, Associate Professor of Microelectronic Engineering


Course Objectives:


1.      Students will learn the CMOS layout levels, how the design layers are used in the process sequence, and resulting device structures (i.e. cross-sectional views).

2.      Students will become familiar with the Mentor Graphics CAD tools through the laboratory exercises.

3.      Students will be able to implement digital logic designs of various types (i.e. combinational logic, multiplexers).

4.      Students will investigate SPICE device models at different levels of complexity.

5.      Students will learn about performance issues and the inherent tradeoffs involved in system design (i.e. power vs. speed).

6.      Students will complete a moderately complex design project that will involve datapath operators, data registers, serial/parallel conversion, clocking/timing details and feedback.

7.      Students will be able to identify the interactions between process parameters, device structures, circuit performance, and system design.


This course provides the students with a hands-on design experience, using CAD tools extensively for schematic capture, functional verification (digital), critical path delay simulation (analog), design layout, design rule checking (DRC) and layout vs. schematic (LVS) verification.  Weekly lab assignments prepare the student for an extensive design project, which must meet specific requirements.  The design project is submitted as a formal report, along with a summary specification table containing the following information:  functional description of the chip (with figure), input requirements (clock, data, reset, etc.), time delay information (input to output), overall size of the design (inside the pad-frame), component breakdown (number of registers, adders, multiplexers, transistors). 


Course Structure:


This 10-week course is comprised of 3 one-hour lectures and a three-hour laboratory session per week.  There is also a weekly recitation for discussion of homework and material review.


Pre- and Co- Requisites


1.      0301-240 Digital Circuits

2.      0301-482 Electronics II

3.      0305-560 Semiconductor Devices II


Course Topics: (lecture hours per topic, 30 total)


1.      Overview of basic MOS devices and processes (2 hrs)

2.      Basic combinational logic gates, synthesis of complex gates, Boolean algebra, Karnaugh map logic reduction (3 hrs)

3.      Details of nMOS and CMOS inverters, DC & Transient analysis (4 hrs)

4.      Logic design methodologies, families of CMOS logic (5 hrs)

5.      Registers and latches, system timing (4hrs)

6.      Control systems - Finite state machines (2 hrs)

7.      Systems & subsystems - logic arrays, ALU's, memory (4hrs)

8.      Performance issues:  Power dissipation, optimizing for system speed, technology scaling (4 hrs)

9.      Design for Testability:  Built-in self test, pseudo-random number generator / signature analysis, boundary-scan design (2 hrs)


Course Topics:  (laboratory hours per topic, 30 total)


1.      Schematic capture, analog/digital circuit simulation, SPICE models (6 hrs)

2.      CMOS inverter simulation: DC & Transient analysis (6 hrs)

3.      CMOS process technology, CMOS layout & design rules, Layout vs. Schematic (6 hrs)

4.      Design, simulation (analog & digital), and layout (LVS) of full-adder and data-flip-flop circuits (6 hrs)

5.      Design project (6 hrs)


Evaluation Methods:


1.      Homework (10%)

2.      Lab reports (15%)

3.      Quizzes (40%)

4.      Final Exam (20%)

5.      Design project (15%)



Lecture:  M & W  10-noon  9-3149

Lab:  ????  VLSI lab