Computer Organization

EECC 550 Winter 2001

MY HOME PAGE RIT Computer Engineering
Final Exam:   Tuesday, May 20, 5:00-7:00pm
BLDG 9   Room 2580 (Xerox Aud.)

Wednesday, 28-Jun-2017 11:48:08 EDT


13 Visitors Since 7-March-2003


  

  Project  ,  Due May 14.
Test Files:
memory.inherent memory.otherbranches memory.otherslogical
memory.othersmath memory.storebranch

  Assignment #1, Due Monday, March 24.

  Assignment #2, Due Wednesday, April 2.

  Assignment #3, Due Wednesday, April 9.

  Assignment #4, Due Monday, May 5.

  Homework Grader:   Douglas   Hoffman  douglas.hoffman@mail.isc.rit.edu

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

3-10-2K3 Introduction to Computer Design, The Design Hierarchy, Technology Trends, Register Transfer Notation (RTN), Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
(Chapters 1, 3)
3-12-2K3 MIPS RISC Instruction Set Architecture: Syntax, Addressing Modes, Instruction Formats, Encoding & Examples.
(Chapter 3)
3-17-2K3 Central Processor Unit (CPU) & Computer System Performance Measures: CPI, CPU Execution Equation, Benchmarking, Amdahl's Law.
(Chapter 2)
3-19-2K3 CPU Design: MIPS Single Cycle Datapath   Control Unit Design.
(Chapter 5.1-5.3)
3-26-2K3 CPU Design: MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
(Chapter 5.4)
4-2-2K3 Microprogrammed CPU Control Design for MIPS. Exception Handling.
(Chapter 5.5, 5.6)
4-9-2K3 CPI Reduction: Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding. Compiler Instruction Scheduling. Delayed Branch. Pipelined CPU Performance.
(Chapter 6)
4-14-2K3 Midterm Review.
4-28-2K3 Removing The Ideal Main Memory Assumption. The Memory Hierarchy: Basic Cache Design & Performance.
(Chapter 7.1-7.3)
5-7-2K3 The Memory Hierarchy: Main & Virtual Memory.
(Chapter 7.4)
5-14-2K3 Final Exam Review.
Get Adobe Acrobat


  

Monday, Wednesday 2:00-3:50PM   Building 9   Room 1159


  

Dr. Muhammad Shaaban
e-mail: meseec@rit.edu
Office: 17-2507 X2373


Office Hours:
My Spring 2003 schedule


  

Current: http://www.rit.edu/~meseec/eecc550-spring2003/
Winter 2002: http://www.rit.edu/~meseec/eecc550-winter2002/
Spring 2002: http://www.rit.edu/~meseec/eecc550-spring2002/
Winter 2001: http://www.rit.edu/~meseec/eecc550-winter2001/
Summer 2001: http://www.rit.edu/~meseec/eecc550-summer2001/
Spring2001: http://www.rit.edu/~meseec/eecc550-spring2001/
Winter2000: http://www.rit.edu/~meseec/eecc550-winter2000/
Summer2000: http://www.rit.edu/~meseec/eecc550-summer2000/
Spring2000: http://www.rit.edu/~meseec/eecc550-spring2000/


  

The course covers the important aspects of the design, organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy, including cache levels and virtual memory.


  

Assembly Programming EECC250,  Introduction to Digital Systems EECC341,  Operating Systems (0603-440).


  

Computer Organization & Design: The Hardware/Software Interface, Second Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 1998


  

Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 30%


  

Attending all lecture sessions is expected.


  

1- Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Notation (RTN).   [Chapters 1, 3]
2- Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC.  [Chapter 3]
3- MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples.   [Chapter 3]
4- Central Processor Unit (CPU) & Computer System Performance Measures.   [Chapter 2]
5- CPU Organization: Datapath & Control Unit Design.   [Chapter 5]
6- Microprogrammed Control Unit Design.   [Chapter 5]
7- CPU Pipelining.   [Chapter 6]
8- The Memory Hierarchy: Cache Design & Performance.  [Chapter 7]
9- The Memory Hierarchy: Main & Virtual Memory.   [Chapter 7]
10- Input/Output Organization & System Performance Evaluation.   [Chapter 8]
11- Computer Arithmetic & ALU Design.   [Chapter 4]

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