EECC550 Spring 2003

Assignment #4
Due Monday, May 5

Solve the following questions:

  1. For the following MIPS code:
    loop:       lw     $1,  0($2)
                lw     $1,  8($1)
                add    $1,  $1, $8
                lw     $3,  0($4)
                lw     $3,  12($3)
                add    $1,  $1,  $3
                addi   $2,  $2,  4
                addi   $4,  $4,  4
                sw     $1,  0($5)
                sub    $6,  $7,  $2
                addi   $5,  $5,  4
                bne    $6,  $0,  loop
    
    Assuming the initial value of   $7 = $2 + 6000 What is the CPI, total number of cycles and execution time when running this code on:
    • Single cycle CPU (chapter 5) with clock cycle = 8ns.
    • Multi-cycle CPU (chapter 5) with clock cycle = 2ns.
    • An ideal pipelined CPU with no stall cycles and clock cycle =2ns.
    • The pipelined CPU without forwarding in Figure 6.30 (page 470) with clock cycle = 2ns.
    • The pipelined CPU with forwarding and reduced branch delay in figure 6.51 (page 499) and clock cycle = 2ns.
    for both pipelined CPUs assume the branch not taken method and include initial pipeline fill cycles.

  2. Schedule the MIPS code given above in question 1 by changing instruction order to minimize stall cycles when running on the pipelined CPU with forwarding and reduced branch delay in figure 6.51 (page 499). Assume a single branch delay slot. What is the CPI, total number of cycles needed to execute the scheduled code? How much faster is the scheduled code compared to the original code?

  3. Chapter 6 exercises in the textbook (pages 530-534):
    Exercises:  4,  11,  12,  14,  15,  23.