Computer Organization

EECC 550 Summer 2001

MY HOME PAGE RIT Computer Engineering
Final Exam:  Wednesday August 15, 5:00 PM
BLDG 17   Room 1545

Tuesday, 19-Sep-2017 13:04:12 EDT


1906 Visitors Since 5-June-2001


  

  Project
Test Files:
memory.inherent memory.otherbranches memory.otherslogical
memory.othersmath memory.storebranch

  Assignment #1, Due Tuesday, June 26.

  Assignment #2, Due Tuesday, July 10.

  Assignment #3, Due Tuesday, August 7.

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

6-5-2K1 Introduction to Computer Design, The Design Hierarchy, Technology Trends, Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
6-7-2K1 MIPS Instruction Set Architecture, Examples, Instruction Formats & Encoding.
6-12-2K1 Computer Performance Measures: CPI, CPU Execution Equation, Benchmarking, Amdahl's Law.
6-14-2K1 MIPS Single Cycle Datapath & Control Unit Design.
6-21-2K1 MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
6-28-2K1 Microprogrammed CPU Control, Exception Handling.
7-17-2K1 Midterm Review.
7-19-2K1 Midterm.
7-24-2K1 Integer ALU Design, Floating Point Computations.
7-26-2K1 CPI Reduction: Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding.
8-2-2K1 The Memory Hierarchy: Basic Cache Design & Performance Issues.
8-9-2K1 he Memory Hierarchy: Main & Virtual Memory.
8-10-2K1 Final Exam Review.
Get Adobe Acrobat


  

Tuesday, Thursday 2:00-3:50 PM Bldg. 17, Room 1545


  

Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373


Office Hours:
My Summer 2001 schedule


  

Current: http://www.rit.edu/~meseec/eecc550-summer2001/
Spring2001: http://www.rit.edu/~meseec/eecc550-spring2001/
Winter2000: http://www.rit.edu/~meseec/eecc550-winter2000/
Summer2000: http://www.rit.edu/~meseec/eecc550-summer2000/
Spring2000: http://www.rit.edu/~meseec/eecc550-spring2000/
Summer 99: http://www.rit.edu/~meseec/eecc550-summer99/
Summer 98: http://www.rit.edu/~meseec/eecc550-summer98/
Summer 97: http://www.rit.edu/~meseec/eecc550/


  

The course covers the important aspects of the design, organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy, including cache levels and virtual memory.


  

Assembly Programming EECC250,  Introduction to Digital Systems EECC341,  Operating Systems (0603-440).


  

Computer Organization & Design: The Hardware/Software Interface, Second Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 1998


  

Participation and class presence: 5%
Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 25%


  

Attending all lecture sessions is expected.


  

1- Introduction: Modern Computer Design Levels, Components, Technology Trends.
2- Instruction Set Architecture (ISA) Characteristics.
3- CPU & Computer System Performance Measures.
4- Hardware Description: Register Transfer Notation (RTN).
5- Central Processor Organization: Datapath & Control Unit Design.
6- Microprogrammed Control Unit Design.
7- Computer Arithmetic & ALU Design.
8- CPU Pipelining.
9- The Memory Hierarchy.
10- I/O Organization: Interfacing Processors and Peripherals.

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