Computer Organization

EECC 550 Winter 2000

MY HOME PAGE RIT Computer Engineering

Wednesday, 24-May-2017 19:22:45 EDT


507 Visitors Since 4-Dec-2000


  

  Assignment #1, Due Monday, December 18.

  Assignment #2, Due Monday, January 8.

  Assignment #3, Due Wednesday, January 17.

  Assignment #4, Due Monday, February 12.

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

12-4-2K Introduction to Computer Design, The Design Hierarchy, Technology Trends, Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
12-6-2K MIPS Instruction Set Architecture, Examples, Instruction Formats & Encoding.
12-11-2K Computer Performance Measures: CPI, CPU Execution Equation, Benchmarking, Amdahl's Law.
12-13-2K MIPS Single Cycle Datapath & Control Unit Design.
12-20-2K MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
1-8-2K1 Microprogrammed CPU Control, Exception Handling.
1-15-2K1 Integer ALU Design, Floating Point Computations.
1-22-2K1 Midterm Review.
1-24-2K1 Instruction Pipelining, Pipeline Hazards, Forwarding.
2-5-2K1 The Memory Hierarchy; Basic Cache Design Issues & Cache Performance.
2-14-2K1 The Memory Hierarchy: Main & Virtual Memory.
2-14-2K1 Final Exam Review.
Get Adobe Acrobat


  

Monday, Wednesday 4:00-5:50 PM Bldg. 9, Room 3149


  

Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373


Office Hours:
My Winter 2000 schedule


  

Current: http://www.rit.edu/~meseec/eecc550-winter2000/
Summer2000: http://www.rit.edu/~meseec/eecc550-summer2000/
Spring2000: http://www.rit.edu/~meseec/eecc550-spring2000/
Summer 99: http://www.rit.edu/~meseec/eecc550-summer99/
Summer 98: http://www.rit.edu/~meseec/eecc550-summer98/
Summer 97: http://www.rit.edu/~meseec/eecc550/


  

The course covers the important aspects of the design, organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy, including cache levels and virtual memory.


  

Assembly Programming EECC250,  Introduction to Digital Systems EECC341,  Operating Systems (0603-440).


  

Computer Organization & Design: The Hardware/Software Interface, Second Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 1998


  

Participation and class presence: 5%
Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 25%


  

Attending all lecture sessions is expected.


  

1- Introduction: Modern Computer Design Levels, Components, Technology Trends.
2- Instruction Set Architecture (ISA) Characteristics.
3- CPU & Computer System Performance Measures.
4- Hardware Description: Register Transfer Notation (RTN).
5- Central Processor Organization: Datapath & Control Unit Design.
6- Microprogrammed Control Unit Design.
7- Computer Arithmetic & ALU Design.
8- CPU Pipelining.
9- The Memory Hierarchy.
10- I/O Organization: Interfacing Processors and Peripherals.

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