Computer Organization

EECC 550 Winter 2001

MY HOME PAGE RIT Computer Engineering
Final Exam:   Thursday, February 27, 8:00 AM
BLDG 9   Room 2129

Wednesday, 24-May-2017 19:14:16 EDT


2467 Visitors Since 5-December-2002


  

  Project
Test Files:
memory.inherent memory.otherbranches memory.otherslogical
memory.othersmath memory.storebranch

  Assignment #1, Due Tuesday, December 17.

  Assignment #2, Due Tuesday, January 7.

  Assignment #3, Due Thursday, January 16.

  Assignment #4, Due Thursday, Februay 13.

  Grader:  Alicia Tyrell  avt6361@rit.edu

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

12-3-2K2 Introduction to Computer Design, The Design Hierarchy, Technology Trends, Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
(Chapters 1, 3)
12-5-2K2 MIPS Instruction Set Architecture, Examples, Instruction Formats & Encoding.
(Chapter 3)
12-12-2K2 Computer Performance Measures: CPI, CPU Execution Equation, Benchmarking, Amdahl's Law.
(Chapter 2)
12-17-2K2 CPU Design: MIPS Single Cycle Datapath & Control Unit Design.
(Chapter 5)
1-7-2K3 MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
(Chapter 5.4)
1-9-2K3 Microprogrammed CPU Control Design. Exception Handling.
(Chapter 5.5, 5.6)
1-21-2K3 Midterm Review.
1-28-2K3 CPI Reduction: Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding. Pipelined CPU Performance.
(Chapter 6)
2-6-2K3 Removing The Ideal Main Memory Assumption. The Memory Hierarchy: Basic Cache Design & Performance.
(Chapter 7.1-7.3)
2-18-2K3 The Memory Hierarchy: Main & Virtual Memory.
(Chapter 7.4)
2-20-2K3 Final Exam Review.
Get Adobe Acrobat


  

Tuesday, Thursday 2:00-3:50PM Building 17 Room 1555


  

Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373


Office Hours:
My Winter 2002 schedule


  

Current: http://www.rit.edu/~meseec/eecc550-winter2002/
Spring 2002: http://www.rit.edu/~meseec/eecc550-spring2002/
Winter 2001: http://www.rit.edu/~meseec/eecc550-winter2001/
Summer 2001: http://www.rit.edu/~meseec/eecc550-summer2001/
Spring2001: http://www.rit.edu/~meseec/eecc550-spring2001/
Winter2000: http://www.rit.edu/~meseec/eecc550-winter2000/
Summer2000: http://www.rit.edu/~meseec/eecc550-summer2000/
Spring2000: http://www.rit.edu/~meseec/eecc550-spring2000/


  

The course covers the important aspects of the design, organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy, including cache levels and virtual memory.


  

Assembly Programming EECC250,  Introduction to Digital Systems EECC341,  Operating Systems (0603-440).


  

Computer Organization & Design: The Hardware/Software Interface, Second Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 1998


  

Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 30%


  

Attending all lecture sessions is expected.


  

1- Introduction: Modern Computer Design Levels, Components, Technology Trends.
2- Instruction Set Architecture (ISA) Characteristics.
3- CPU & Computer System Performance Measures.
4- Hardware Description: Register Transfer Notation (RTN).
5- Central Processor Organization: Datapath & Control Unit Design.
6- Microprogrammed Control Unit Design.
7- CPU Pipelining.
8- The Memory Hierarchy.
9- I/O Organization: Interfacing Processors and Peripherals.
10- Computer Arithmetic & ALU Design.

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