Computer Organization

EECC 550 Winter 2005

MY HOME PAGE RIT Computer Engineering
Final Exam:   Thursday, March 2, 12:30-2:30PM
       Building 9   Room 1149

Monday, 20-Nov-2017 00:54:01 EST


21 Visitors Since 28-Nov-2005


  

  Project  ,  Due February 23.
Project Test Files:
memory.inherent memory.otherbranches memory.otherslogical
memory.othersmath memory.storebranch

  Assignment #1, Due Thursday, December 15.

  Assignment #2, Due Tuesday, January 10.

  Assignment #3, Due Tuesday, January 24.

  Assignment #4, Due Thursday, February 16.

  Assignment #5, Do Not Submit.

  Homework Grader:   Eric Ernst   Email: ege8200@rit.edu

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

11-29-2K5 Introduction to Computer Design, The Design Hierarchy, Technology Trends, Register Transfer Notation (RTN), Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
(Chapters 1, 2)
12-1-2K5 MIPS RISC Instruction Set Architecture: Syntax, Addressing Modes, Instruction Formats, Encoding & Examples.
(Chapter 2)
12-6-2K5 Central Processor Unit (CPU) & Computer System Performance Measures: CPI, CPU Execution Equation, Benchmarking, MIPS Rating, Amdahl's Law.
(Chapter 4)
12-13-2K5 CPU Design: MIPS Single Cycle Datapath, Control Unit Design.
(Chapter 5.1-5.4)
1-10-2K6 CPU Design: MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
(Chapter 5.5)
1-17-2K6 Microprogrammed CPU Control Design for MIPS. Exception Handling.
(Microprogramming: 5.7, Appendix C.   Exception Handling: Chapter 5.6)
1-19-2K6 Selected Chapter 5 "For More Practice" Exercises.
1-24-2K6 Midterm Review.
1-31-2K6 Microprogramming Project.
2-2-2K6 CPI Reduction: CPU Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding. Compiler Instruction Scheduling. Delayed Branch. Pipelined CPU Performance.
(Chapter 6.1-6.6)
2-9-2K6 Removing The Ideal Main Memory Assumption. The Memory Hierarchy: Basic Cache Design & Performance.
(Chapter 7.1-7.3)
2-21-2K6 The Memory Hierarchy: Main & Virtual Memory. (FYI)
(Chapter 7.3-7.4)
2-23-2K6 Final Exam Review.
Get Adobe Acrobat


  

Tuesday, Thursday 2:00-3:50PM   Building 9   Room 2159


  

Dr. Muhammad Shaaban
e-mail: meseec@rit.edu
Office: 17-2507 475-2373


Office Hours:
My Winter 2005 schedule


  

Current: http://www.rit.edu/~meseec/eecc550-winter2005/
Winter 2004: http://www.rit.edu/~meseec/eecc550-winter2004/
Winter 2003: http://www.rit.edu/~meseec/eecc550-winter2003/
Spring 2003: http://www.rit.edu/~meseec/eecc550-spring2003/
Winter 2002: http://www.rit.edu/~meseec/eecc550-winter2002/
Spring 2002: http://www.rit.edu/~meseec/eecc550-spring2002/
Winter 2001: http://www.rit.edu/~meseec/eecc550-winter2001/
Summer 2001: http://www.rit.edu/~meseec/eecc550-summer2001/
Spring2001: http://www.rit.edu/~meseec/eecc550-spring2001/
Winter2000: http://www.rit.edu/~meseec/eecc550-winter2000/
Summer2000: http://www.rit.edu/~meseec/eecc550-summer2000/
Spring2000: http://www.rit.edu/~meseec/eecc550-spring2000/


  

The course covers the important aspects of the design, organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy, including cache levels and virtual memory.


  

Assembly Programming EECC250,  Introduction to Digital Systems EECC341,  Operating Systems (0603-440).


  

Computer Organization & Design: The Hardware/Software Interface, Third Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 2004


  

Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 30%


  

Attending all lecture sessions is expected.


  

1- Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Notation (RTN).   [Chapters 1, 2]
2- Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC.  [Chapter 2]
3- MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples.   [Chapter 2]
4- Central Processor Unit (CPU) & Computer System Performance Measures.   [Chapter 4]
5- CPU Organization: Datapath & Control Unit Design.   [Chapter 5]
6- Microprogrammed Control Unit Design.   [Chapter 5]
7- CPU Pipelining.   [Chapter 6]
8- The Memory Hierarchy: Cache Design & Performance.  [Chapter 7]
9- The Memory Hierarchy: Main & Virtual Memory.   [Chapter 7]
10- Input/Output Organization & System Performance Evaluation.   [Chapter 8]
11- Computer Arithmetic & ALU Design.   [Chapter 3]

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