Computer Organization

EECC 550 Winter 2007

MY HOME PAGE RIT Computer Engineering
Final Exam:   Tuesday, February 26, 8:00-10:00AM
       Building 9   Room 2139

Sunday, 25-Aug-2019 08:20:15 EDT

1922 Visitors Since 30-Nov-2007


  Project  ,  Due February 21.
Project Test Files:
memory.inherent memory.otherbranches memory.otherslogical
memory.othersmath memory.storebranch

  Assignment #1, Due Thursday, December 20.

  Assignment #2, Due Thursday, January 10.

  Assignment #3, Due Tuesday, January 22.

  Assignment #4, Due Thursday, February 14.

  Assignment #5, Do Not Submit.


For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

12-4-2K7 Introduction to Computer Design, The Design Hierarchy, Technology Trends, Register Transfer Notation (RTN), Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
(Chapters 1, 2)
12-6-2K7 MIPS RISC Instruction Set Architecture: Syntax, Addressing Modes, Instruction Formats, Encoding & Examples.
(Chapter 2)
12-11-2K7 Central Processor Unit (CPU) & Computer System Performance Measures: CPI, CPU Execution Equation, Benchmarking, MIPS Rating, Amdahl's Law.
(Chapter 4)
12-18-2K7 CPU Design: MIPS Single Cycle Datapath, Control Unit Design.
(Chapter 5.1-5.4)
1-10-2K8 CPU Design: MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
(Chapter 5.5)
1-15-2K8 Microprogrammed CPU Control Design for MIPS. Exception Handling.
(Microprogramming: 5.7, Appendix C.   Exception Handling: Chapter 5.6)
1-17-2K8 Microprogramming Project.
1-22-2K8 Midterm Review.
1-29-2K8 CPI Reduction: CPU Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding. Compiler Instruction Scheduling. Delayed Branch. Pipelined CPU Performance.
(Chapter 6.1-6.6)
2-7-2K8 Removing The Ideal Main Memory Assumption. The Memory Hierarchy: Basic Cache Design & Performance.
(Chapter 7.1-7.3)
2-19-2K8 Input/Output & System Performance Issues. (FYI)
(Chapter 8)
2-21-2K8 Final Exam Review.
Get Adobe Acrobat


Tuesday, Thursday 2:00-3:50PM   Building 9   Room 1149


Dr. Muhammad Shaaban
Office: 9-3469 475-2373

Office Hours:
My Winter 2007 schedule


Winter 2006:
Winter 2005:
Winter 2004:
Winter 2003:
Spring 2003:
Winter 2002:
Spring 2002:
Winter 2001:
Summer 2001:


The course covers the important aspects of the design, organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy, including cache levels and virtual memory.


Assembly Programming EECC250,  Introduction to Digital Systems EECC341,  Operating Systems (0603-440).


Computer Organization & Design: The Hardware/Software Interface, Third Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 2004


Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 30%


Attending all lecture sessions is expected.


1- Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Notation (RTN).   [Chapters 1, 2]
2- Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC.  [Chapter 2]
3- MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples.   [Chapter 2]
4- Central Processor Unit (CPU) & Computer System Performance Measures.   [Chapter 4]
5- CPU Organization: Datapath & Control Unit Design.   [Chapter 5]
6- Microprogrammed Control Unit Design.   [Chapter 5]
7- CPU Pipelining.   [Chapter 6]
8- The Memory Hierarchy: Cache Design & Performance.  [Chapter 7]
9- The Memory Hierarchy: Main & Virtual Memory.   [Chapter 7]
10- Input/Output Organization & System Performance Evaluation.   [Chapter 8]
11- Computer Arithmetic & ALU Design.   [Chapter 3]

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