Computer Organization

EECC 550 Winter 2011

MY HOME PAGE RIT Computer Engineering
Final Exam:   Thursday, March 1st, 12:30-2:30PM
       Building 9   Room 1139

Monday, 20-Nov-2017 00:49:48 EST


1922 Visitors Since 23-Nov-2011


  

  Project  ,  Due 12:00 Noon Monday, February 27.
Project Zipped File (also in myCourses page)

  Assignment #1, Due Thursday, December 15.

  Assignment #2, Due Thursday, January 12.

  Assignment #3, Due Thursday, January 19.

  Assignment #4, Due Tuesday, February 14.

  Assignment #5, Do Not Submit.

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

11-29-2011 Introduction to Computer Design, The Design Hierarchy, Technology Trends, Register Transfer Notation (RTN), Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
(Chapters 1, 2)
12-1-2011 MIPS RISC Instruction Set Architecture: Syntax, Addressing Modes, Instruction Formats, Encoding & Examples.
(Chapter 2)
12-6-2011 Central Processor Unit (CPU) & Computer System Performance Measures: CPI, CPU Execution Equation, Benchmarking, MIPS Rating, Amdahl's Law.
(4th Edition: Chapter 1  -  3rd Edition: Chapter 4)
12-13-2011 CPU Design: MIPS Single Cycle Datapath, Control Unit Design.
(4th Edition: Chapter 4.1-4.4  -  3rd Edition: Chapter 5.1-5.4)
1-10-2012 CPU Design: MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
(3rd Edition Chapter 5.5 - See handout - Not in 4th Edition)
1-17-2012 Microprogrammed CPU Control Design for MIPS. Exception Handling.
(3rd Edition - Microprogramming: 5.7, Appendix C.   Exception Handling: Chapter 5.6 - See Handout - Not in 4th Edition )
1-19-2012 Effective CPI Reduction: CPU Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding. Compiler Instruction Scheduling. Delayed Branch. Pipelined CPU Performance.
(4th Edition: Chapter 4.5-4.8  -  3rd Edition: Chapter 6.1-6.6)
1-24-2012 Midterm Review.
1-24-2012 Microprogramming Project.
2-7-2012 Removing The Ideal Main Memory Assumption. The Memory Hierarchy: Basic Cache Design & Performance.
(4th Edition: Chapter 5.1-5.3  -  3rd Edition: Chapter 7.1-7.3)
2-16-2012 The Memory Hierarchy: Main & Virtual Memory. (FYI)
(4th Edition: Chapter 5.2-5.4  -  3rd Edition: Chapter 7.3-7.4)
2-21-2012 Final Exam Review + Course Evaluation


  

Tuesday, Thursday 4:00-5:50PM   Building 9 (GLE)   Room 1139


  

Dr. Muhammad Shaaban
e-mail: meseec@rit.edu
Office: 9-3469 475-2373


Office Hours:
My Winter 2011 schedule


  

Current: http://people.rit.edu/meseec/eecc550-winter2011/
Winter 2010: http://people.rit.edu/meseec/eecc550-winter2010/
Winter 2009: http://people.rit.edu/meseec/eecc550-winter2009/
Winter 2008: http://people.rit.edu/meseec/eecc550-winter2008/
Winter 2007: http://people.rit.edu/meseec/eecc550-winter2007/
Winter 2006: http://people.rit.edu/meseec/eecc550-winter2006/
Winter 2005: http://people.rit.edu/meseec/eecc550-winter2005/
Winter 2004: http://people.rit.edu/meseec/eecc550-winter2004/
Winter 2003: http://people.rit.edu/meseec/eecc550-winter2003/
Spring 2003: http://people.rit.edu/meseec/eecc550-spring2003/
Winter 2002: http://people.rit.edu/meseec/eecc550-winter2002/
Spring 2002: http://people.rit.edu/meseec/eecc550-spring2002/
Winter 2001: http://people.rit.edu/meseec/eecc550-winter2001/
Summer 2001: http://people.rit.edu/meseec/eecc550-summer2001/
Spring2001: http://people.rit.edu/meseec/eecc550-spring2001/
Winter2000: http://people.rit.edu/meseec/eecc550-winter2000/
Summer2000: http://people.rit.edu/meseec/eecc550-summer2000/
Spring2000: http://people.rit.edu/meseec/eecc550-spring2000/


  

The course covers the important aspects of the design, organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic unit design, and the memory hierarchy, including cache levels and virtual memory.


  

Assembly Programming EECC250,  Introduction to Digital Systems EECC341,  Operating Systems (0603-440).


  

Computer Organization & Design: The Hardware/Software Interface, Fourth Edition, David Patterson and John Hennessy, Morgan Kaufmann Publishers, 2008.


  

Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 30%


  

Attending all lecture sessions is expected.


  

1- Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Notation (RTN).   [Chapters 1, 2]
2- Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC.  [Chapter 2]
3- MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples.   [Chapter 2]
4- Central Processor Unit (CPU) & Computer System Performance Measures.   [Chapter 4]
5- CPU Organization: Datapath & Control Unit Design.   [Chapter 5]
6- Microprogrammed Control Unit Design.   [Chapter 5]
7- CPU Pipelining.   [Chapter 6]
8- The Memory Hierarchy: Cache Design & Performance.  [Chapter 7]
9- The Memory Hierarchy: Main & Virtual Memory.   [Chapter 7]
10- Input/Output Organization & System Performance Evaluation.   [Chapter 8]
11- Computer Arithmetic & ALU Design.   [Chapter 3]

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