RIT Computer Engineering


Tuesday, 23-Jul-2019 18:06:00 EDT

15 Visitors Since 4-Sep-2001


   Assignment #1, Due Thursday, September 20.

   Assignment #2, Due Tuesday, October 2.

   Assignment #3, Due Thursday, October 25.

   Assignment #4, Due Thursday, November 1.


For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

9-6-2K1 Basics of Computer Design. Performance Measures. Instruction Set Architecture Characteristics and Classifications. CISC vs. RISC, The DLX Architecture.
9-11-2K1 A basic Multi-Cycle Implementation of DLX, Introduction to Pipelining: Definitions, Performance, A pipelined DLX, Pipeline Hazard Classification, Data Forwarding. Data Hazards, Control Hazards, Static Branch Prediction, Compiler Pipeline Scheduling, Instruction Pipelining and Exception Handling.
9-18-2K1 Floating Point/Multicycle Pipelining, Exploiting Instruction-Level Parallelism (ILP): Loop Unrolling, Classification of Instruction Dependencies, Loop-Level Parallelism (LLP) Analysis.
9-25-2K1 Dynamic Hardware-Based Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach.
10-2-2K1 Dynamic Hardware-Based Branch Prediction Techniques: Branch-Target Buffer (BTB), Branch History Table (BHT), Correlating Two-Level Dynamic Branch Predictors.
10-11-2K1 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Speculation: Software, Hardware. ILP Compiler Support, GCD Test.
10-16-2K1 The Memory Hierarchy. Cache Design Considerations: Organization, Replacement Policy, Write Strategies, Performance.
10-18-2K1 3Cs of Cache, Cache Performance Optimization Techniques; Reduction of: Miss Rate, Miss Penalty and Hit Time.
10-25-2K1 The Memory Hierarchy: Main & Virtual Memory.
11-1-2K1 I/O Sub-System Design Considerations: I/O Performance Metrics, Disk Storage Parameters, Bus Characteristics, Queuing Theory Modeling of I/O.
11-6-2K1 Exam Review.


4:00-5:50 PM Tuesday, Thursday in room 17/1555


Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373

Office Hours:
My Fall 2001 schedule


Current: http://www.rit.edu/~meseec/eecc551-fall2001/
Winter 2000: http://www.rit.edu/~meseec/eecc551-winter2000/
Fall 2000: http://www.rit.edu/~meseec/eecc551-fall2000/
Winter 99: http://www.rit.edu/~meseec/eecc551-winter99/
Fall 99: http://www.rit.edu/~meseec/eecc551-fall99/
Winter 98: http://www.rit.edu/~meseec/eecc551-winter98/
Fall98: http://www.rit.edu/~meseec/eecc551-fall98/
Winter 97: http://www.rit.edu/~meseec/eecc551-winter97/
Fall 97: http://www.rit.edu/~meseec/eecc551-fall97/


The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


Computer Organization EECC550(0306-550).


Computer Architecture: A Quantitative Approach, Second Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, 1996.
Selected papers.

Memory Latency: to Tolerate or to Reduce?


Participation and class presence: 5%
Homework assignments: 30%
Exam: 35%
Special topics project: 30%


Attending all lecture sessions is expected.


Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The DLX Architecture.
Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling.
Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis.
Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach.
Week5: Dynamic Hardware-based Branch Prediction.
Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support.
Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance.
Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues.
Week9: Project Presentations.

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