RIT Computer Engineering


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Exam & Presentations

   Exam Review   Thursday Oct. 31  (4:00pm, in class)

   Exam:   Tuesday Nov. 5
           2:00-3:50 PM in room   8/3154
           4:00-5:50 PM in room   9/2159

   Presentations 1:   Thursday Nov. 7
           4:00-5:50 PM in room   9/2159

   Presentations 2:   Tuesday Nov. 12
           3:00-5:50 PM in room   9/2159

   Presentations 3:   Nov. 14 (reading day)
           1:00-3:50 PM in room   9/2139


   Assignment #1, Due Thursday, September 19.

   Assignment #2, Due Thursday, October 10.

   Assignment #3, Due Thursday, October 24.


For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

9-5-2K2 Basics of Computer Design. Performance Measures. Instruction Set Architecture (ISA) Characteristics and Classifications. CISC vs. RISC, The MIPS64 ISA. (Chapters 1,2)
9-10-2K2 Pipelining Review: Definitions, Performance, Classic 5-stage Integer Pipeline, Pipeline Hazard Classification, Data Forwarding. Compiler Pipeline Scheduling. Static Branch Prediction, Branch Delay Slot. MIPS R4000. Instruction Pipelining and Exception Handling. (Appendix A)
9-12-2K2 Floating Point/Multicycle Pipelining, Exploiting Instruction-Level Parallelism (ILP): Loop Unrolling, Further Classification of Instruction Dependencies, (Appendix A.5,  Ch 3.1  Ch 4.1)
9-19-2K2 Dynamic Hardware-Based Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach. (Appendix A.8,  Ch 3.2,  3.3)
9-26-2K2 Dynamic Hardware-Based Branch Prediction Techniques: Branch-Target Buffer (BTB), Single-level, Correlating Two-Level, Gshare, and Hybrid Dynamic Branch Predictors. Comparison of Branch Prediction Implementations. (Ch 3.4, 3.5)
10-3-2K2 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Speculation: Software, Hardware. Speculative Tomasulo Algorithm. (Ch 3.6,  3.7,  4.3,  4.5)
10-10-2K2 Loop-Level Parallelism (LLP) Analysis. GCD Test. Software Pipelining. (Ch 4.4)
10-15-2K2 The Memory Hierarchy: Review of Cache Organization, Replacement Policy, Write Strategies, & Performance. Multi-Level Cache. (Ch 5.1-5.3)
10-17-2K2 The Memory Hierarchy: Main & Virtual Memory. (Ch 5.8-5.10)
10-24-2K2 Input/Output & System Performance Issues. (Ch. 7.1-7.3, 7.7, 7.8)
10-31-2K2 Exam Review


4:00-5:50 PM Tuesday, Thursday in room 9/2159


Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373

Office Hours:
My Fall 2002 schedule


Current: http://www.rit.edu/~meseec/eecc551-fall2002/
Winter 2001: http://www.rit.edu/~meseec/eecc551-winter2001/
Fall 2001: http://www.rit.edu/~meseec/eecc551-fall2001/
Winter 2000: http://www.rit.edu/~meseec/eecc551-winter2000/
Fall 2000: http://www.rit.edu/~meseec/eecc551-fall2000/
Winter 99: http://www.rit.edu/~meseec/eecc551-winter99/
Fall 99: http://www.rit.edu/~meseec/eecc551-fall99/


The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


Computer Organization EECC550(0306-550).


Computer Architecture: A Quantitative Approach, Third Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, May 2002.
Selected papers.


Homework assignments: 25%
Exam: 45%
Special topics project: 30%


Attending all lecture sessions is expected.


Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The MIPS64 Architecture.
Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling.
Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis.
Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach.
Week5: Dynamic Hardware-based Branch Prediction.
Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support.
Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance.
Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues.
Week9: Project Presentations.

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