RIT Computer Engineering


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Exam & Presentations

   Exam:   Tuesday, November 8
           2:00PM   in 9/3400.
           (CE Senior Projects Lab)

   Presentations 1:   Thursday, November 10
           2:00-3:50PM in 9/1139.
           (normal lecture time/room)

   Presentations 2: Tuesday, November 15
           1:00-4:00PM in 9/2129




For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint file:

9-6-2011 Basics of Computer Design. Performance Measures. Instruction Set Architecture (ISA) Characteristics and Classifications. CISC vs. RISC, The MIPS64 ISA.
(Fourth Edition: Chapter 1, Appendix B,   Third Edition: Chapters 1, 2)
9-8-2011 Pipelining Review: Definitions, Performance, Classic 5-stage Integer Pipeline, Pipeline Hazard Classification, Data Forwarding. Compiler Pipeline Scheduling. Static Branch Prediction, Branch Delay Slot. MIPS R4000. Instruction Pipelining and Exception Handling. Floating Point/Multicycle Pipelining
(Both Editions: Appendix A)
9-15-2011 Exploiting Instruction-Level Parallelism (ILP): Basic Instruction Block, Loop Unrolling. Further Classification of Instruction Dependencies: Dependency Analysis and Graphs.
(Fourth Edition: Chapter 2.1, 2.2,   Third Edition: Chapter 3.1, 4.1)
9-20-2011 Dynamic Hardware-Based Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach.
(Fourth Edition: Appendix A.7, Chapter 2.4, 2.5,   Third Edition: Appendix A.8, Chapter 3.2, 3.3)
A Tomasulo Simulator from UMass
9-27-2011 Fundamental Dynamic Hardware-Based Branch Prediction Techniques: Branch-Target Buffer (BTB), Single-level, Correlating Two-Level, Gshare, and Hybrid Dynamic Branch Predictors.
(Fourth Edition: Chapter 2.3, 2.9,   Third Edition: Chapter 3.4, 3.5, 4.2)
9-29-2011 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Hardware-Based Speculation: Speculative Tomasulo.
(Fourth Edition: Chapter 2.6-2.8, Third Edition: Chapter 3.6, 3.7, 4.3)
10-11-2010 Data Parallelism & Loop-Level Parallelism (LLP) Analysis. GCD Test. Software Pipelining.
FYI: Brief Introduction to Vector Processing.
Fourth Edition: Appendix G.1-3, Third Edition: Chapter 4.4)
Vector Processing:Appendix G (3rd ed.), Appendix F (4th ed.)
10-13-2011 Review of Memory Hierarchy & Cache Basics (from 550). 3Cs of Cache Misses, Cache Write Strategies & Performance. Multi-Level Cache.
(Fourth Edition: Chapter 5.1, Appendix C.1-C.3   Third Edition: Chapter 5.1-5.4)
10-25-2011 Input/Output & System Performance Issues.
(Fourth Edition: Chapter 6.1, 6.2, 6.4, 6.5   Third Edition: Chapter 7.1-7.3, 7.7, 7.8)
11-1-2011 The Memory Hierarchy: Main Memory Issues. Performance Metrics: Latency & Bandwidth. DRAM System Memory Generations. Basic Memory Bandwidth Improvement/Miss Penalty Reduction Techniques.
(Fourth Edition: Chapter 5.3   Third Edition: Chapter 5.8, 5.9)
11-3-2011 Exam Review.


2:00-3:50 PM Tuesday and Thursday in 9/1139


Dr. Muhammad Shaaban
e-mail: meseec@rit.edu
Office: 9-3469 X52373

Office Hours:
My Fall 2011 schedule


Quizzes/Homework: 40%
Exam: 35%
Special Topic paper and presentation: 25%

Quizzes are announced one class in advance, and are given only during first 20-30 minutes of the specified class. Quizzes are closed references (e.g. no books, notes, handouts, etc...). Calculators will be helpful. There are no makeup quizzes and your lowest quiz grade is automatically excluded from the average calculation.

2-hour Exam:
A single all-inclusive 2-hour examination is given in week 10. Books, notes, quizzes and handouts are allowed in the exam. A calculator will be very helpful.

Special Topic paper and presentation:
Students will select one partner from the class to research a significant topic in the field of Computer Architecture, write a report, and give a presentation. Each groupís topic must be presented and approved by Dr. Shaaban. Duplicate topics are not permitted and proposals are accepted on a first come first serve basis.

The Paper: Each group will write a joint report (~ 6-8 pages) on their research using the IEEE journal format/guidelines/template. DO NOT CHANGE THE TEMPLATE! Take great care in following the guidelines, especially properly citing illustrations, graphs and quoting from their respective sources. The paper is due (hardcopy and electronic) at the beginning of the last day of the presentations. Late submissions will be significantly penalized. Plagiarism will result in a Zero ( see page 18 of the KGCOE 2011-2012 Student Handbook).

The Presentation: Each group will give a 20-minute PowerPoint presentation of their research to the entire class. This is a joint presentation and the group must be thoroughly prepared to answer questions. A signup sheet for a time slot will be available towards the end of the quarter. Attendance is mandatory for all presentation sessions. Missing your presentation slot and/or electronic submission time will result in a zero. You must submit your Microsoft Power Point presentation electronically to Dr. Shaaban 24 hrs prior to your presentation time slot. Samples of prior presentations are available on the course website.


Current: http://people.rit.edu/meseec/eecc551-fall2011/
Spring 2011: http://people.rit.edu/meseec/eecc551-spring2011/
Winter 2010: http://people.rit.edu/meseec/eecc551-winter2010/
Fall 2010: http://people.rit.edu/meseec/eecc551-fall2010/
Spring 2010: http://people.rit.edu/meseec/eecc551-spring2010/
Winter 2009: http://people.rit.edu/meseec/eecc551-winter2009/
Fall 2009: http://people.rit.edu/meseec/eecc551-fall2009/
Spring 2009: http://people.rit.edu/meseec/eecc551-spring2009/
Winter 2008: http://people.rit.edu/meseec/eecc551-winter2008/
Fall 2008: http://people.rit.edu/meseec/eecc551-fall2008/
Spring 2008: http://people.rit.edu/meseec/eecc551-spring2008/
Winter 2007: http://people.rit.edu/meseec/eecc551-winter2007/
Fall 2007: http://people.rit.edu/meseec/eecc551-fall2007/
Spring 2007: http://people.rit.edu/meseec/eecc551-spring2007/
Winter 2006: http://people.rit.edu/meseec/eecc551-winter2006/
Fall 2006: http://people.rit.edu/meseec/eecc551-fall2006/
Spring 2006: http://people.rit.edu/meseec/eecc551-spring2006/
Winter 2005: http://people.rit.edu/meseec/eecc551-winter2005/
Fall 2005: http://people.rit.edu/meseec/eecc551-fall2005/
Spring 2005: http://people.rit.edu/meseec/eecc551-spring2005/
Winter 2004: http://people.rit.edu/meseec/eecc551-winter2004/
Fall 2004: http://people.rit.edu/meseec/eecc551-fall2004/
Spring 2004: http://people.rit.edu/meseec/eecc551-spring2004/
Winter 2003: http://people.rit.edu/meseec/eecc551-winter2003/
Fall 2003: http://people.rit.edu/meseec/eecc551-fall2003/
Winter 2002: http://people.rit.edu/meseec/eecc551-winter2002/
Fall 2002: http://people.rit.edu/meseec/eecc551-fall2002/
Winter 2001: http://people.rit.edu/meseec/eecc551-winter2001/
Fall 2001: http://people.rit.edu/meseec/eecc551-fall2001/
Winter 2000: http://people.rit.edu/meseec/eecc551-winter2000/
Fall 2000: http://people.rit.edu/meseec/eecc551-fall2000/
Winter 99: http://people.rit.edu/meseec/eecc551-winter99/
Fall 99: http://people.rit.edu/meseec/eecc551-fall99/


The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


Computer Organization EECC550(0306-550).


Computer Architecture: A Quantitative Approach, Fourth Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, 2006.

Reference Papers:

  • Virtual Memory:

    1. Virtual memory: Issues of implementation, PDF,
      B. Jacob,