RIT Computer Engineering


Sunday, 25-Aug-2019 07:10:13 EDT

5 Visitors Since 5-Sep-1999


   Assignment #1, Due Thursday, September 23.

   Assignment #2, Due Monday, October 4.

   Assignment #3, Due Wednesday, October 13.

   Assignment #4, Due Monday, October 25.


For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

9-6-99 Basics of Computer Design. Performance Measures.
9-8-99 Instruction Set Architecture Characteristics and Classifications. CISC vs. RISC, The DLX Architecture.
9-13-99 A basic Multi-Cycle Implementation of DLX, Introduction to Pipelining: Definitions, Performance, A pipelined DLX, Pipeline Hazard Classification, Data Forwarding
9-20-99 Data Hazards, Control Hazards, Static Branch Prediction, Compiler Pipeline Scheduling, Instruction Pipelining and Exception Handling.
9-21-99 Floating Point/Multicycle Pipelining, Exploiting Instruction-Level Parallelism (ILP): Loop Unrolling, Classification of Instruction Dependencies, Loop-Level Parallelism (LLP) Analysis,
9-29-99 Dynamic Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach.
10-5-99 Dynamic Branch Prediction Techniques: Branch History Table (BHT), Correlating Two-Level Dynamic Branch Predictors, Branch-Target Buffers.
10-11-99 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Speculation: Software, Hardware. ILP Compiler Support, GCD Test.
10-13-99 The Memory Hierarchy. Cache Design Considerations: Organization, Replacement Policy, Write Strategies, Performance.
10-18-99 3Cs of Cache, Cache Performance Optimization Techniques; Reduction of: Miss Rate, Miss Penalty and Hit Time
10-20-99 The Memory Hierarchy: Main & Virtual Memory
10-27-99 I/O Sub-System Design Considerations: Disk Storage Parameters, Bus Characteristics, I/O Performance Measures, Little's queueing theory.
11-1-99 Simultaneous Multithreading (SMT).


Monday, Wednesday 10:00 AM - 11:50 AM 17/1545


Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373

Office Hours:
My Fall 99 schedule


Current: http://www.rit.edu/~meseec/eecc551-fall99/
Winter 98: http://www.rit.edu/~meseec/eecc551-winter98/
Fall98: http://www.rit.edu/~meseec/eecc551-fall98/
Winter 97: http://www.rit.edu/~meseec/eecc551-winter97/
Fall 97: http://www.rit.edu/~meseec/eecc551-fall97/


The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


Computer Organization EECC550(0306-550).


Computer Architecture: A Quantitative Approach, Second Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, 1996.
Selected papers.


Participation and class presence: 5%
Homework assignments: 30%
Exam: 35%
Special topics project: 30%


Attending all lecture sessions is expected.


Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The DLX Architecture.
Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling.
Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis.
Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach.
Week5: Dynamic Hardware-based Branch Prediction.
Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support.
Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance.
Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues.
Week9: Project Presentations.

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