RIT Computer Engineering


Sunday, 25-Aug-2019 07:49:27 EDT

2440 Visitors Since 11-March-2006

Exam & Presentations

   Exam:   Monday, May 15
           3:00-6:00 PM in 17/1555

   Presentations 1:   Wednesday, May 17
           4:00-5:50 PM in 9/3129
           (normal lecture time/room)

   Presentations 2: Friday, May 19
           1:00-3:00 PM in 9/2139

   Presentations 3: Monday, May 22
           2:45-4:45 PM in 9/2139




For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

3-13-2K6 Basics of Computer Design. Performance Measures. Instruction Set Architecture (ISA) Characteristics and Classifications. CISC vs. RISC, The MIPS64 ISA.
(Chapters 1,  2)
3-15-2K6 Pipelining Review: Definitions, Performance, Classic 5-stage Integer Pipeline, Pipeline Hazard Classification, Data Forwarding. Compiler Pipeline Scheduling. Static Branch Prediction, Branch Delay Slot. MIPS R4000. Instruction Pipelining and Exception Handling. Floating Point/Multicycle Pipelining
(Appendix A)
3-20-2K6 Exploiting Instruction-Level Parallelism (ILP): Basic Instruction Block, Loop Unrolling. Further Classification of Instruction Dependencies: Dependency Analysis and Graphs.
(Chapter 3.1, Chapter 4.1)
3-27-2K6 Dynamic Hardware-Based Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach.
(Appendix A.8, Chapter 3.2, 3.3)
4-3-2K6 Dynamic Hardware-Based Branch Prediction Techniques: Branch-Target Buffer (BTB), Single-level, Correlating Two-Level, Gshare, and Hybrid Dynamic Branch Predictors. Comparison of Branch Prediction Implementations.
(Chapter 3.4, 3.5, 4.2)
4-10-2K6 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Speculation: Software, Hardware. Speculative Tomasulo Algorithm.
(Chapter 3.6, 3.7, 4.3, 4.5)
4-17-2K6 Data Parallelism & Loop-Level Parallelism (LLP) Analysis. GCD Test. Software Pipelining. Brief Introduction to Vector Processing.
(Chapter 4.4, Appendix G)
4-19-2K6 Review of Memory Hierarchy & Cache Basics (from 550). 3Cs of Cache Misses, Cache Write Strategies & Performance. Multi-Level Cache.
(Chapter 5.1-5.3)
5-1-2K6 Input/Output & System Performance Issues.
(Chapter 7.1-7.3, 7.7, 7.8)
5-8-2K6 The Memory Hierarchy: Main Memory Issues. Performance Metrics: Latency & Bandwidth. DRAM System Memory Generations. Basic Memory Bandwidth Improvement/Miss Penalty Reduction Techniques.
(Chapter 5.8-5.10)
5-10-2K6 Exam Review.
5-10-2K6 The Memory Hierarchy: Virtual Memory Issues.   (FYI)
(Chapter 5.10-5.11, 2 Virtual Memory Reference Papers)


4:00-5:50 PM Monday, Wednesday in room 9/3129


Dr. Muhammad Shaaban
e-mail: meseec@rit.edu
Office: 17-2507 X52373

Office Hours:
My Spring 2006 schedule


Quizzes/Homework: 40%
Exam: 35%
Special Topic paper and presentation: 25%

Quizzes are announced one class in advance, and are given only during first 20-30 minutes of the specified class. Quizzes are closed references (e.g. no books, notes, handouts, etc...). Calculators will be helpful. There are no makeup quizzes and your lowest quiz grade is automatically excluded from the average calculation.

2-hour Exam:
A single all-inclusive 2-hour examination is given in week 10. Books, notes, quizzes and handouts are allowed in the exam. A calculator will be very helpful.

Special Topic paper and presentation:
Students will select one partner from the class to research a significant topic in the field of Computer Architecture, write a report, and give a presentation. Each groupís topic must be presented and approved by Dr. Shaaban. Duplicate topics are not permitted and proposals are accepted on a first come first serve basis.

The Paper: Each group will write a joint report (~ 8-15 pages) on their research using the IEEE journal format/guidelines/template. DO NOT CHANGE THE TEMPLATE! Take great care in following the guidelines, especially properly citing illustrations, graphs and quoting from their respective sources. The paper is due (hardcopy and electronic) at the beginning of the last day of the presentations. Late submissions will be significantly penalized. Plagiarism will result in a Zero ( see page 19 of the KGCOE 2005-2006 Student Handbook).

The Presentation: Each group will give a 20-minute PowerPoint presentation of their research to the entire class. This is a joint presentation and the group must be thoroughly prepared to answer questions. A signup sheet for a time slot will be available towards the end of the quarter. Attendance is mandatory for all presentation sessions. Missing your presentation slot and/or electronic submission time will result in a zero. You must submit your Microsoft Power Point presentation electronically to Dr. Shaaban 24 hrs prior to your presentation time slot. Samples of prior presentations are available on the course website.


Current: http://www.rit.edu/~meseec/eecc551-spring2006/
Winter 2005: http://www.rit.edu/~meseec/eecc551-winter2005/
Fall 2005: http://www.rit.edu/~meseec/eecc551-fall2005/
Spring 2005: http://www.rit.edu/~meseec/eecc551-spring2005/
Winter 2004: http://www.rit.edu/~meseec/eecc551-winter2004/
Fall 2004: http://www.rit.edu/~meseec/eecc551-fall2004/
Spring 2004: http://www.rit.edu/~meseec/eecc551-spring2004/
Winter 2003: http://www.rit.edu/~meseec/eecc551-winter2003/
Fall 2003: http://www.rit.edu/~meseec/eecc551-fall2003/
Winter 2002: http://www.rit.edu/~meseec/eecc551-winter2002/
Fall 2002: http://www.rit.edu/~meseec/eecc551-fall2002/
Winter 2001: http://www.rit.edu/~meseec/eecc551-winter2001/
Fall 2001: http://www.rit.edu/~meseec/eecc551-fall2001/
Winter 2000: http://www.rit.edu/~meseec/eecc551-winter2000/
Fall 2000: http://www.rit.edu/~meseec/eecc551-fall2000/
Winter 99: http://www.rit.edu/~meseec/eecc551-winter99/
Fall 99: http://www.rit.edu/~meseec/eecc551-fall99/


The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


Computer Organization EECC550(0306-550).


Computer Architecture: A Quantitative Approach, Third Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, May 2002.

Reference Papers:

  • Virtual Memory:

    1. Virtual memory: Issues of implementation, PDF,
      B. Jacob, and T. Mudge,
      Computer, vol. 31, no. 6, pp. 33-43. June 1998.

    2. Virtual memory in contemporary microprocessors, PDF,
      B. Jacob, and T. Mudge,
      Micro, vol. 18, no. 4, pp. 60-75. July/Aug. 1998.

  • I/O Performance, RAID, Unix I/O Performance:

    1. Maximizing Performance in a Striped Disk Array, PDF,
      P. Chen and D.A. Patterson,
      Proc. 17th Annual IEEE Symposium on Computer Architecture, 1990, pp. 322-331.

    2. Storage Performance--Metrics and Benchmarks, PDF,
      P. Chen and D. Patterson,
      Proceedings of the IEEE 81(8):1151-1165, Aug., 1993.

    3. RAID: HighPerformance, Reliable Secondary Storage, PDF,
      P. M. Chen, E. K. Lee, G. A. Gibson, R. H. Katz and D. A. Patterson,
      ACM Computing Surveys, Vol.26, No.2, June 1994, pp.145-185.

    4. Unix I O Performance in Workstations and Mainframes, PDF,
      Peter M. Chen, David A. Patterson,
      Dept. of Electrical Engr. and Computer Science, University of Michigan, Technical Report, CSE-TR-200-94, 1994.

    5. Striping in a RAID Level 5 Disk Array, PDF,
      P. Chen, P.M., AND E. Lee,
      Proc. 1995 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pp.136---145, May 1995.

  • Vector Processing, Vector IRAM:

    1. Vector Processors, PDF, Appendix G, Computer Architecture: A Quantitative Approach, Third Edition.

    2. Scalable Processors in the Billion Transistor Era: IRAM, PDF,
      Christoforos E. Kozyrakis et al.
      IEEE Computer Special Issue: Future Microprocessors - How to use a Billion Transistors, September 1997.


Attending all lecture sessions is expected.


Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The MIPS64 Architecture.
Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling.
Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis.
Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach.
Week5: Dynamic Hardware-based Branch Prediction.
Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support.
Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance.
Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues.
Week9: Introduction to parallel processing and multiprocessor system architecture.
Week10-11: Exam/Project Presentations.

  This page is 28Kbytes long and was last modified on:   Monday, 25-Feb-2008 17:16:43 EST.

Made with at least 30% post-consumer recycled bits