RIT Computer Engineering

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New Room: Building 8, Room 1300


Wednesday, 24-May-2017 19:15:43 EDT


15 Visitors Since 30-Nov-2000



  

   Assignment #1, Due Thursday, December 14.

   Assignment #2, Due Tuesday, January 9.

   Assignment #3, Due Thursday, January 25.

   Assignment #4, Due Tuesday, February 13.

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

11-30-2K Basics of Computer Design. Performance Measures.
12-5-2K Instruction Set Architecture Characteristics and Classifications. CISC vs. RISC, The DLX Architecture.
12-7-2K A basic Multi-Cycle Implementation of DLX, Introduction to Pipelining: Definitions, Performance, A pipelined DLX, Pipeline Hazard Classification, Data Forwarding.
12-12-2K Data Hazards, Control Hazards, Static Branch Prediction, Compiler Pipeline Scheduling, Instruction Pipelining and Exception Handling.
12-14-2K Floating Point/Multicycle Pipelining, Exploiting Instruction-Level Parallelism (ILP): Loop Unrolling, Classification of Instruction Dependencies, Loop-Level Parallelism (LLP) Analysis.
12-19-2K Dynamic Hardware-Based Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach.
1-9-2K1 Dynamic Hardware-Based Branch Prediction Techniques: Branch History Table (BHT), Correlating Two-Level Dynamic Branch Predictors, Branch-Target Buffer.
1-11-2K1 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Speculation: Software, Hardware. ILP Compiler Support, GCD Test.
1-16-2K1 The Memory Hierarchy. Cache Design Considerations: Organization, Replacement Policy, Write Strategies, Performance.
1-23-2K1 3Cs of Cache, Cache Performance Optimization Techniques; Reduction of: Miss Rate, Miss Penalty and Hit Time.
1-25-2K1 The Memory Hierarchy: Main & Virtual Memory.
2-1-2K1 I/O Sub-System Design Considerations: Disk Storage Parameters, Bus Characteristics, I/O Performance Metrics, Queuing Theory Modeling of I/O.
2-8-2K1 Redundant Array of Inexpensive Disks (RAID), I/O Benchmarks, ABCs of UNIX File Systems, A study of UNIX File I/O Perormance.
2-13-2K1 Exam Review.


  

4:00-5:50 PM Tuesday, Thursday in room 9/3119


  

Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373


Office Hours:
My Winter 2000 schedule


  

Current: http://www.rit.edu/~meseec/eecc551-winter2000/
Fall 2000: http://www.rit.edu/~meseec/eecc551-fall2000/
Winter 99: http://www.rit.edu/~meseec/eecc551-winter99/
Fall 99: http://www.rit.edu/~meseec/eecc551-fall99/
Winter 98: http://www.rit.edu/~meseec/eecc551-winter98/
Fall98: http://www.rit.edu/~meseec/eecc551-fall98/
Winter 97: http://www.rit.edu/~meseec/eecc551-winter97/
Fall 97: http://www.rit.edu/~meseec/eecc551-fall97/


  

The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


  

Computer Organization EECC550(0306-550).


  

Computer Architecture: A Quantitative Approach, Second Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, 1996.
Selected papers.

Memory Latency: to Tolerate or to Reduce?


  

Participation and class presence: 5%
Homework assignments: 30%
Exam: 35%
Special topics project: 30%


  

Attending all lecture sessions is expected.


  

Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The DLX Architecture.
Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling.
Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis.
Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach.
Week5: Dynamic Hardware-based Branch Prediction.
Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support.
Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance.
Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues.
Week9: Project Presentations.

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