Thursday, 21-Jun-2018 21:29:02 EDT
For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:
2:00-3:50 PM Monday in room 12/1135, Wednesday in room 9/3129
Dr. Muhammad Shaaban
Office: 17-2507 X2373
My Winter 2001 schedule
Fall 2001: http://www.rit.edu/~meseec/eecc551-fall2001/
Winter 2000: http://www.rit.edu/~meseec/eecc551-winter2000/
Fall 2000: http://www.rit.edu/~meseec/eecc551-fall2000/
Winter 99: http://www.rit.edu/~meseec/eecc551-winter99/
Fall 99: http://www.rit.edu/~meseec/eecc551-fall99/
Winter 98: http://www.rit.edu/~meseec/eecc551-winter98/
Winter 97: http://www.rit.edu/~meseec/eecc551-winter97/
Fall 97: http://www.rit.edu/~meseec/eecc551-fall97/
he course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.
Computer Organization EECC550(0306-550).
Computer Architecture: A Quantitative Approach, Second Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, 1996.
Homework assignments: 25%
Special topics project: 30%
Attending all lecture sessions is expected.
Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The DLX Architecture. Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling. Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis. Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach. Week5: Dynamic Hardware-based Branch Prediction. Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support. Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance. Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues. Week9: Project Presentations.