RIT Computer Engineering


Tuesday, 23-Jul-2019 18:50:21 EDT

11 Visitors Since 3-Dec-2001

Exam & Presentations

   Exam:   Monday 2-18   2:00PM  Building  7  Room  1350
      (For those starting the exam at noon, meet in my office)

   Presentations 1:  Wednesday 2-20   1:00PM   Building  9  Room  2580 (Xerox Aud.)

   Presentations 2:  Friday 2-22   1:00PM   Building  6  Room   A201


   Assignment #1, Due Wednesday, December 19.

   Assignment #2, Due Wednesday, January 9.

   Assignment #3, Due Monday, January 28.


For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

12-3-2K1 Basics of Computer Design. Performance Measures. Instruction Set Architecture Characteristics and Classifications. CISC vs. RISC, The DLX Architecture.
12-5-2K1 A basic Multi-Cycle Implementation of DLX, Introduction to Pipelining: Definitions, Performance, A pipelined DLX, Pipeline Hazard Classification, Data Forwarding. Data Hazards, Control Hazards, Static Branch Prediction, Compiler Pipeline Scheduling, Instruction Pipelining and Exception Handling.
12-10-2K1 Floating Point/Multicycle Pipelining, Exploiting Instruction-Level Parallelism (ILP): Loop Unrolling, Classification of Instruction Dependencies, Loop-Level Parallelism (LLP) Analysis.
12-17-2K1 Dynamic Hardware-Based Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach.
1-9-2K2 Dynamic Hardware-Based Branch Prediction Techniques: Branch-Target Buffer (BTB), Branch History Table (BHT), Correlating Two-Level Dynamic Branch Predictors.
1-16-2K2 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Speculation: Software, Hardware. Speculative Tomasulo Algorithm, ILP Compiler Support, GCD Test.
1-23-2K2 The Memory Hierarchy: Review of Cache Organization, Replacement Policy, Write Strategies, & Performance.
1-30-2K2 3Cs of Cache, Cache Performance Optimization Techniques; Reduction of: Miss Rate, Miss Penalty and Hit Time.
2-4-2K2 The Memory Hierarchy: Main & Virtual Memory.
2-11-2K2 Input/Output & System Performance Issues.


2:00-3:50 PM Monday in room 12/1135, Wednesday in room 9/3129


Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373

Office Hours:
My Winter 2001 schedule


Current: http://www.rit.edu/~meseec/eecc551-winter2001/
Fall 2001: http://www.rit.edu/~meseec/eecc551-fall2001/
Winter 2000: http://www.rit.edu/~meseec/eecc551-winter2000/
Fall 2000: http://www.rit.edu/~meseec/eecc551-fall2000/
Winter 99: http://www.rit.edu/~meseec/eecc551-winter99/
Fall 99: http://www.rit.edu/~meseec/eecc551-fall99/
Winter 98: http://www.rit.edu/~meseec/eecc551-winter98/
Fall98: http://www.rit.edu/~meseec/eecc551-fall98/
Winter 97: http://www.rit.edu/~meseec/eecc551-winter97/
Fall 97: http://www.rit.edu/~meseec/eecc551-fall97/


The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


Computer Organization EECC550(0306-550).


Computer Architecture: A Quantitative Approach, Second Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, 1996.
Selected papers.


Homework assignments: 25%
Exam: 45%
Special topics project: 30%


Attending all lecture sessions is expected.


Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The DLX Architecture.
Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling.
Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis.
Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach.
Week5: Dynamic Hardware-based Branch Prediction.
Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support.
Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance.
Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues.
Week9: Project Presentations.

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