RIT Computer Engineering


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Exam & Presentations

   Exam Review   Wednesday Feb. 12  (2:00pm, in class)

   Exam:   Monday Feb. 17
           1:00-5:00 PM in room   9/2271

   Presentations 1:  + Course Evaluation   Wednesday Feb. 19
           2:00-4:00 PM in room   9/1149
           4:00-5:00 PM in room   9/3149

   Presentations 2:   Friday Feb. 21
           2:00-5:00 PM in room   9/1139


   Assignment #1, Due Wednesday, December 11.

   Assignment #2, Due Wednesday, January 8.

   Assignment #3, Due Monday, January 27.


For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

12-2-2K2 Basics of Computer Design. Performance Measures. Instruction Set Architecture (ISA) Characteristics and Classifications. CISC vs. RISC, The MIPS64 ISA. (Chapters 1,2)
12-4-2K2 Pipelining Review: Definitions, Performance, Classic 5-stage Integer Pipeline, Pipeline Hazard Classification, Data Forwarding. Compiler Pipeline Scheduling. Static Branch Prediction, Branch Delay Slot. MIPS R4000. Instruction Pipelining and Exception Handling. Floating Point/Multicycle Pipelining (Appendix A)
12-9-2K2 Exploiting Instruction-Level Parallelism (ILP): Loop Unrolling, Further Classification of Instruction Dependencies.
(Chapter 3.1,  Chapter 4.1)
12-16-2K2 Dynamic Hardware-Based Instruction Pipeline Scheduling: The Scoreboard, The Tomasulo Approach.
(Appendix A.8,  Ch 3.2,  3.3)
1-6-2K3 Dynamic Hardware-Based Branch Prediction Techniques: Branch-Target Buffer (BTB), Single-level, Correlating Two-Level, Gshare, and Hybrid Dynamic Branch Predictors. Comparison of Branch Prediction Implementations.
(Ch 3.4, 3.5)
1-8-2K3 Multiple Instruction Issue, CPI <1 Approaches: Superscalar, VLIW. Speculation: Software, Hardware. Speculative Tomasulo Algorithm.
(Ch 3.6, 3.7, 4.3, 4.5)
1-13-2K3 Loop-Level Parallelism (LLP) Analysis. GCD Test. Software Pipelining.
(Ch 4.4)
1-15-2K3 The Memory Hierarchy: Review of Cache Organization, Replacement Policy, Write Strategies, & Performance. Multi-Level Cache.
(Ch 5.1-5.3)
1-20-2K3 3Cs of Cache, Cache Performance Optimization Techniques; Reduction of: Miss Rate, Miss Penalty and Hit Time.
(Ch 5.4-5.7)
1-22-2K3 The Memory Hierarchy: Main & Virtual Memory.
(Ch 5.8-5.10, Reference Papers Below)
1-29-2K3 Input/Output & System Performance Issues.
(Ch. 7.1-7.3, 7.7, 7.8)
2-5-2K3 Redundant Array of Inexpensive Disks (RAID), I/O Benchmarks, ABCs of UNIX File Systems, A study of UNIX File I/O Perormance.
(Ch. 7.4, 7.5, 7.9, Reference Papers Below)
2-10-2K3 Vector Processing: Basics and Architectures. Vector Intelligent RAM (VIRAM)
(From EECC722 Fall 2002, Appendix G, See references below)
2-12-2K3 Exam Review


2:00-3:50 PM
Monday:  building 6 room 3201
Wednesday:  building 9 room 1149


Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373

Office Hours:
My Winter 2002 schedule


Current: http://www.rit.edu/~meseec/eecc551-winter2002/
Fall 2002: http://www.rit.edu/~meseec/eecc551-fall2002/
Winter 2001: http://www.rit.edu/~meseec/eecc551-winter2001/
Fall 2001: http://www.rit.edu/~meseec/eecc551-fall2001/
Winter 2000: http://www.rit.edu/~meseec/eecc551-winter2000/
Fall 2000: http://www.rit.edu/~meseec/eecc551-fall2000/
Winter 99: http://www.rit.edu/~meseec/eecc551-winter99/
Fall 99: http://www.rit.edu/~meseec/eecc551-fall99/


The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed. Techniques to enhance performance such as pipelined execution optimizations, branch-handling, exploiting instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. Finally, the design of efficient and reliable input/output systems are covered.


Computer Organization EECC550(0306-550).


Computer Architecture: A Quantitative Approach, Third Edition, John Hennessy, and David Patterson, Morgan Kaufmann Publishers, May 2002.

Reference Papers:

  • Virtual Memory:

    1. Virtual memory: Issues of implementation, PDF,
      B. Jacob, and T. Mudge,
      Computer, vol. 31, no. 6, pp. 33-43. June 1998.

    2. Virtual memory in contemporary microprocessors, PDF,
      B. Jacob, and T. Mudge,
      Micro, vol. 18, no. 4, pp. 60-75. July/Aug. 1998.

  • I/O Performance, RAID, Unix I/O Performance:

    1. Maximizing Performance in a Striped Disk Array, PDF,
      P. Chen and D.A. Patterson,
      Proc. 17th Annual IEEE Symposium on Computer Architecture, 1990, pp. 322-331.

    2. Storage Performance--Metrics and Benchmarks, PDF,
      P. Chen and D. Patterson,
      Proceedings of the IEEE 81(8):1151-1165, Aug., 1993.

    3. RAID: HighPerformance, Reliable Secondary Storage, PDF,
      P. M. Chen, E. K. Lee, G. A. Gibson, R. H. Katz and D. A. Patterson,
      ACM Computing Surveys, Vol.26, No.2, June 1994, pp.145-185.

    4. Unix I O Performance in Workstations and Mainframes, PDF,
      Peter M. Chen, David A. Patterson,
      Dept. of Electrical Engr. and Computer Science, University of Michigan, Technical Report, CSE-TR-200-94, 1994.

    5. Striping in a RAID Level 5 Disk Array, PDF,
      P. Chen, P.M., AND E. Lee,
      Proc. 1995 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pp.136---145, May 1995.

  • Vector Processing, Vector IRAM:

    1. Vector Processors, PDF, Appendix G, Computer Architecture: A Quantitative Approach, Third Edition.

    2. Scalable Processors in the Billion Transistor Era: IRAM, PDF,
      Christoforos E. Kozyrakis et al.
      IEEE Computer Special Issue: Future Microprocessors - How to use a Billion Transistors, September 1997.


Homework assignments: 25%
Exam: 45%
Special topics project: 30%


Attending all lecture sessions is expected.


Week1: Fundamentals of Computer Architecture Design, Performance Measures Review. Instruction Set Principles Review and Examples. CISC vs. RISC. A Typical RISC Example: The MIPS64 Architecture.
Week2: CPU Pipelining Concepts Review, Pipeline Hazards. Branch Handling: Static branch prediction Static Compiler pipeline scheduling. Pipelining and Exception Handling.
Week3: Advanced Pipelining, Exploiting Instruction-Level Parallelism (ILP). Pipeline Scheduling, Loop Unrolling. Instruction Dependencies Analysis.
Week4: Dynamic Instruction Scheduling: The Scoreboard Approach, The Tomasulo Approach.
Week5: Dynamic Hardware-based Branch Prediction.
Week6: Exploiting ILP Further: Multiple-Instruction Issue Approaches: Superscalar, VLIW. Software and hardware Speculation. Compiler ILP support.
Week7: Cache Design Issues, Memory-Hierarchy Design. Advanced Techniques to Improve Cache Performance.
Week8: Storage Systems, Bus Design, I/O Performance Measures and Benchmarks Reliable Storage: Redundant Array of Inexpensive Disks (RAID). I/O System Design Issues.
Week9: Project Presentations.

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