Research and Publications
Regarding research, my interests focus on heterogeneous computing, or how to make CPU, GPU and reconfigurable hardware work together to provide best performance. Programability is a challenge, but even before that, finding out the key phases of an application and the best hardware matches for their requirements is an important design issue that needs to be addressed. Data transfers among hardware choices, bandwidth management and memory hierarchy are also key pieces of this kind of hardware solutions. All of this while keeping track of power consumption.
Kate Gleason College of Engineering, Student Engagement in Research Award 2015
Recent Journal Publications and Book Chapters:
Heterogeneous Photonic Network-on-Chip with Dynamic Bandwidth Allocation, N. Mansor, S. Lopez, A. Ganguli. Advances in GPU Research and Practice, Elsevier, November 2015.
Design and Performance Analysis of Efficient KECCAK Tree Hashing on GPU Architectures. J. Lowden, M. Lukowiak, S. Lopez. Journal of Computer Security, December 2015.
Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs.S. Skalicky, S. Lopez, M. Lukowiak. Computers and Electrical Engineering. January 2014.
Peer-reviewed Conference Publications:
Alternative Processor within Threshold: Flexible Scheduling on Heterogeneous Systems. S. Karia and S. Lopez. Heterogeneity in Computing Workshop, International Parallel & Distributed Processing Symposium, May 2017
Power Analysis of HLS-Designed Customized Instruction Set Architectures. T. Ananthanarayana, S. Lopez, M. Lukowiak. Reconfigurable Architectures Workshop, International Parallel & Distributed Processing Symposium, May 2017
Designing Customized ISA Processors Using High Level Synthesis. S. Skalicky, T. Ananthanarayana, S. Lopez, M. Lukowiak. International Conference on ReConFigurable Computing and FPGAs. December 2015.
A Parallelizing Matlab Compiler Framework and Run time for Heterogeneous Systems. S. Skalicky, S. Lopez, M. Lukowiak and A. Schmidt. International Conference on High Performance Computing and Communications, HPCC. August, 2015.
Impact of Partitioning Cache Schemes on the Cache Hierarchy of SMT processors. S. Kenyon, S. Lopez and J. Sahuquillo. International Conference on High Performance Computing and Communications, HPCC. August, 2015. Invited paper.
A Unified Hardware/Software MPSoC System Construction and Run-time Framework. S. Skalicky, A. Schmidt, M. French, S. Lopez. Design, Automation and Test in Europe, DATE. March 2015.
Mission Control: A Performance Metric and Analysis of Control Logic for Pipelined Architectures on FPGAs. S. Skalicky, S. Lopez and M. Lukowiak. International Conference on ReConFigurable Computing and FPGAs. December 2014.
Enabling FPGA support in Matlab based Heterogeneous Systems. S. Skalicky, T. Kwolek, S. Lopez and M.Lukowiak. International Conference on ReConFigurable Computing and FPGAs. December 2014.
Satisfying Bandwidth Requirements of GPU Architectures through Adaptive Wavelength Division Multiplexing. B. Johnstone and S. Lopez Alarcon. International Green Computing Conference. November 2014. Heterogeneous Photonic Network-on-Chip with Dynamic Bandwidth Allocation. N. Mansoor, A. Ganguly, s. Lopez, B. Johnstone. System On Chip Conference, September 2014.
Distributed Execution of Transmural Electrophysiological Imaging with CPU, GPU, and FPGA. S. Skalicky, S. Lopez, M. Lukowiak. International Conference on ReConFigurable Computing and FPGAs. December 2013.
Drowsy cache Partitioning for Reduced Static and Dynamic Energy in the Cache Hierarchy. B. Fitzgerald, S. Lopez, J. Sahuquillo. International Green computing Conference. July 2013.
Linear Algebra Computations in Heterogeneous Systems. S. Skalicky, S. Lopez, M. Lukowiak, J. Letendre. Application-Specific system, Architectures and Processors. June 2013.
Performance Modeling of Pipelined Architectures on FPGAs. S. Skalicky, S. Lopez, M. Lukowiak, J. Letendre and M. Ryan. International Symposium on Applied Reconfigurable Computing, March 2013.
A Comparison of Sequential and GPU-Accelerated Implementations of B-Spline Signal Processing Operations for 2-D and 3-D Images. A. Karantza, S. Lopez and N. D. Cahill. International Conference on Image Processing Theory, Tools and Applications, October 2012.
GPU Acceleration of Transmural Electrophysiological Imaging. M. Corraine, S. Lopez, L. Wang. Computing in Cardiology, September 2012.
Low Bandwidth Eye Tracker for Scanning Laser Ophthalmoscopy. Z. Harvey, A. Dubra, N. Cahill. S. Lopez. SPIE Medical Image, February 2012.
Efficient Resource Management for Cloud Computing Environments. A. J. Younge, G.von Laszewski, L. Wang, S. Lopez Alarcon, W. Carithers. Green Computing Conference, August 2010.
Adaptive Cache Memories for SMT Processors. S. Lopez O. Garnica. D. H. Albonesi, S. Dropsho, J. Lanchares, J. I. Hidalgo. Euromicro Conference on Digital System Design, 2010.
Improving SMT Performance: an Application of Genetic Algorithms to Configure Resizable Caches. J. DÃaz, J. Ignacio Hidalgo, F. FernÃ¡ndez, O. Garnica, S. LÃ³pez. Late-Breaking Paper, Genetic and Evolutionary Computation Conference, 2009.
Applying Genetic Algorithms to Resizable Caches Configuration for Improving SMT Performance. J. DÃaz, J. Ignacio Hidalgo, F. FernÃ¡ndez , O. Garnica, S. LÃ³pez. Second Workshop on Parallelism and Bioinspired Algorithms, 2009.
Rate-Driven Control of Resizable Caches for Highly Threaded SMTProcessors. S. Lopez, S. Dropsho, D. Albonesi, O. Garnica and J. Lanchares. PACT, Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, 2007.
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. S. Lopez, S.Dropsho, D. Albonesi, O. Garnica and J. Lanchares. International Conference on High Performance Embedded Architectures & Compilers, 2007.
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. G.MiÃ±ana, J.I. Hidalgo, O. Garnica, J. Lanchares, J.M. Colmenar and S. LÃ³pez. International Workshop on Power and Timing Modeling, Optimization and Simulation, 2006.
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. J.M. Colmenar, O. Garnica, J. Lanchares, J.I. Hidalgo, G. MiÃ±ana and S. LÃ³pez. 9th Euromicro Conference on Digital System Design, 2006.
Sim-async: an Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. J.M. Colmenar, O. Garnica, J. Lanchares, J.I. Hidalgo, G. MiÃ±ana and S. LÃ³pez. Euro-Par, 2006.
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. S. LÃ³pez, O. Garnica and J.M. Colmenar. International Workshop on Power and Timing Modeling, Optimization and Simulation, 2004.
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. J.M. Colmenar, O. Garnica, S. LÃ³pez, J. I. Hidalgo, J. Lanchares and R. Hermida. Parallel, Distributed and Network-based Processing, 2004.
Power-consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization. S. LÃ³pez, O. Garnica, J.I. Hidalgo, J. Lanchares and R. Hermida. International Workshop on Power and Timing Modeling, Optimization and Simulation, 2003.